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Ã0#8à à!0` !8ä ¬ ¬ ¬ $ûÿüÿ ¬ Ã0#8à à!0` !8ä $þÿüÿ ¬ À!8Ä $þÿÿÿ à <èÿ½' $ ¿¯ ø 0 ¥0Â@ < B$ @ ø@ ùÿ ``AÀ ª<¿<Ufc$0ò@¬0òC¬fU<ªc40òC¬¿< $öC¬¿<öBY@ <èÿ½' B$ @ ¿¯ < B$ @ <? p <\B$ ø@ <èÿ½' B$ @ ¿¯ < B$ @ <? p <\B$ ø@ h@ <%b h@ $¿< àC¬¿< àC¬ < B$ @ < B$ @ <? p <\B$ ø@ 0 à ``A à ``Aøÿ$ @$b B4 à @øÿ$ @$b B4 à @ `@¿ÿ<ÿÿ{7$Ð[ `@ B à H@ à `bA à `bA à à<Z' @ @ @ @ @ @ @ @ @ @ @ @ @@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @@ @ @ @ ê@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @`@ÀZ @ <¼Z' @ <ðÿ½' <ð'` @ X *}II}`@À àÜA`@À <ü% ø < % < )% %+ ùÿ <Ô% % % ` % ÿÿJ% % ,¡ûÿ@ )% ¡ÿÿJ%ýÿ@ )% %üÿ$$@H çÿ < )% < )%¿< J% I < )%¿< J% I < )%¿<0 J% I H@ÿÿ$ X@À < )%x@ < )%$DI*}`@ < h@ @ }@L `@X <$@%@( `@ <% ø `@¿ÿ<ÿÿ!4$@ `@ 0 ¥0 <% < Z' @ ø@À <\{' À@ ø@À Bÿÿÿ:Ùyøÿ[Ìtÿ÷ÿÿGCC: (Microchip Technology) 4.5.2 MPLAB XC32 v1.31 Compiler GCC: (Microchip Technology) 4.5.2 MPLAB XC32 Compiler v1.20 libc/arch/mips/memset.S GCC: (Microchip Technology) 4.5.2 MPLAB XC32 Compiler v1.30 ò Èb ä $ rc ¤ 1d 0ãd ì e ô Mf p g 8 ág ü h Yi Ø 8 3j @ 0 1 ò È Delay_MS Delay_US d main £ ò ÖA e4 VA_TO_PA ¢4 ETH_Init 85 ETH_PHY_Read }5 ETH_PHY_Write Ï5 ETH_Recv_Queue ñ5 ETH_Read_Packet |6 ETH_Write_Packet 27 __ETH_Interrupt_Handler Èb ª ReadCoreTimer 7 rc ¿ CheKseg0CacheOff CheKseg0CacheOn % 1d ² INTConfigureSystem & ãd ´ INTEnableInterrupts ' e ¶ INTDisableInterrupts ' Mf ¶ INTRestoreInterrupts / g Þ ² _bootstrap_exception_handler ág ¸ _on_reset h À £ _on_bootstrap - Yi Ú ° _general_exception_handler $ 3j Ò ± _DefaultInterrupt î GNU C 4.5.2 MPLAB XC32 v1.31 Compiler main.c C:/Users/Kevin/Documents/Code/Cerebot_MX7CK_Ethernet unsigned int OE RTCOE P{ # HALFSEC Q{ # RTCSYNC R{ # RTCWREN S{ # RTCCLKON U{ # RTSECSEL V{ # SIDL X{ # ON Z{ # CAL [{# ]] w ^{ # Np E __RTCCONbits_t `] g ARPT h{ # AMASK i{ # ALRMSYNC j{ # PIV k{ # CHIME l{ # ALRMEN m{ # o w p{ # f- __RTCALRMbits_t r ë WAITE { # WAITM { # WAITB { # MODE { # MODE16 { # INCM { # IRQM { # BUSY { # WAITE0 { # WAITE1 { # WAITM0 { # WAITM1 { # WAITM2 { # WAITM3 { # WAITB0 { # WAITB1 { # MODE0 { # MODE1 { # INCM0 { # INCM1 { # IRQM0 { # IRQM1 { # / w { # H D ë __PMMODEbits_t ¡ / F OSWEN G { # SOSCEN H { # UFRCEN I { # CF J { # SLPEN K { # SLOCK L { # ULOCK M { # CLKLOCK N { # NOSC O { # COSC Q { # PLLMULT S { # PBDIV T { # SOSCRDY V { # FRCDIV X { # PLLODIV Y { # [ NOSC0 ] { # NOSC1 ^ { # NOSC2 _ { # COSC0 a { # COSC1 b { # COSC2 c { # PLLMULT0 e { # PLLMULT1 f { # PLLMULT2 g { # PBDIV0 h { # PBDIV1 i { # FRCDIV0 k { # FRCDIV1 l { # FRCDIV2 m { # PLLODIV0 n { # PLLODIV1 o { # PLLODIV2 p { # r - w s { #E F _ __OSCCONbits_t u - VEC { # SRIPL { # __INTSTATbits_t !] Xì DMABUSY Z{ # SUSPEND [{ # ON ]{ # _ w `{ #W ¥ ì __DMACONbits_t b {Ø CRCCH |{ # CRCTYP ~{ # CRCAPP { # CRCEN { # PLEN { # BITO { # WBO { # BYTO { # ò w { #z 1 Ø __DCRCCONbits_t ò ³(TRISG0 ´{ # TRISG1 µ{ # TRISG2 ¶{ # TRISG3 ·{ # TRISG6 ¹{ # TRISG7 º{ # TRISG8 »{ # TRISG9 ¼{ # TRISG12 ¾{ # TRISG13 ¿{ # TRISG14 À{ # TRISG15 Á{ # ÃBw Ä{ #²V(__TRISGbits_t ÆBçj LATG0 è{ # LATG1 é{ # LATG2 ê{ # LATG3 ë{ # LATG6 í{ # LATG7 î{ # LATG8 ï{ # LATG9 ð{ # LATG12 ò{ # LATG13 ó{ # LATG14 ô{ # LATG15 õ{ # ÷ w ø{ #æ lj __LATGbits_t ú Y RXBUSY [{ # TXBUSY \{ # BUSY ]{ # BUFCNT _{ # a) ETHBUSY c{ # eC w f{ #X\ ) __ETHSTATbits_t hC ~ Ö MIIMBUSY { # SCAN { # NOTVALID { # LINKFAIL { # ð w { #} t Ö __EMACxMINDbits_t ð long unsigned int long int int char short unsigned int short intÞ¼ INT_SYSTEM_CONFIG_MULT_VECTOR INT_SYSTEM_CONFIG_SINGLE_VECTOR signed char long long int UINT T{ unsigned char long long unsigned int NT reg PT # clr QT #set RT #inv ST # Ü REG_SET T PV¶ mode X¶ # sta Y¶ #tx Z¶ # rx [¶ #0brg \¶ #@ Y UART_REGS ]h __uint8_t /è __uint32_t 3{ ^ BYTE_0 Ì # BYTE_1 !Ì #BYTE_2 "Ì #BYTE_3 #Ì #BYTE_4 $Ì #BYTE_5 %Ì # y ï bytes 'y Ì ETH_MAC_ADDRESS (^ +K Ì -{ # COLLISION_COUNT .{ # À /{ # 0{# Ê 1{ # DONE 2{ # MULTICASE 3{ # ¬ 4{ # PACKET_DEFER 5{ # EXCESSIVE_DEFER 6{ # MAXIMUM_COLLISION 7{ # LATE_COLLISION 8{ # GIANT 9{ # UNDERRUN :{ # BYTES_TRANSMITTED <{ #w ={ #ò >{ #BACKPRESSURE ?{ #Y @{ # *d e Cd Ý t ETH_TRANSMIT_STATUS_VECTOR DK Gÿ Ì I{ # LONG_DROP_EVENT J{ # RXDV_EVENT K{ # CARRIER_EVENT L{ # CODE_VIOLATION M{ # À N{ # O{# Ê P{ # RECEIVE_OK Q{ # MULTICAST R{ # ¬ S{ # DRIBBLE_NIBBLE T{ # w U{ # ò V{ # UNKNOWN_OP_CODE W{ # Y X{ # PKT_CHECKSUM [{ #RUNT_PACKET ]{ #BROADCAST_OR_NOT_DEST ^{ #HASH_TABLE_MATCH _{ #MAGIC_PACKET_MATCH `{ #PATTERN_MATCH a{ #UNICAST_MATCH b{ #BROADCAST_MATCH c{ #MULTICAST_MATCH d{ # F e fd ETH_RECEIVE_STATUS_VECTOR gÿ i´ EOWN k{ # NPV l{ # Ì n{ # EOP p{ # SOP q{ # M rÝ #TSV st # ETH_TX_ETHERNET_DESCRIPTOR t9 vQ EOWN x{ # NPV y{ # Ì {{ # EOP }{ # SOP ~{ # M Ý #RSV # ETH_RX_ETHERNET_DESCRIPTOR Ö $ ÿ # next_ED Ý # ´ ¬ ETH_TX_DESCRIPTOR_TABLE s $ ô ÿ ô # next_ED Ý # Q ETH_RX_DESCRIPTOR_TABLE Ë ô TX_ED_table¬ # RX_ED_table #$TX_ED_buffer ô #HRX_ED_buffer ô #¨ TX_descriptor_index Ì #@RX_descriptor_index Ì #@tx_callback #@rx_callback #@ Ì ï ETH_DATA # DmaSuspend [? M suspSt ]? DmaResume yp susp y? OSCSetPBDIV ©Ã oscPbDiv ©{ dma_status «{ !. ¬{ oscBits F "SYSTEMConfigPB l{ #£ l{ pb_div n{ !é o{ "SYSTEMConfigWaitStatesAndPB Ò{ d #£ Ò{ wait_states Õ{ !é ×{ !. Ø{ SYSTEMConfigPerformance { È $£ { pb_clk { cache_status { %. { &Delay_MS ) n 'delay_ms )Ý (delay ,Ý ) -Ý &Delay_US 1 nd 'delay_us 1Ý (delay 4Ý ) 5Ý *main 9? n# (eth_data S à (buffer W# ôÀ (dest ^ ¬Ø (src _ ´Ø +d 4 , -4 < . Ô .¦ Ü .» Ø / 4 < ,/ -4 Ì .: Ì .M È .XÐ /à 4 Ì ,à $-4 Ì .ë ,.ù (/p | È , 0-| È . <.¨ 4.³ ¼Ø +# Ì È - Ì .= 8 /M P ¼ ,b À /# \ ¤ -\ ¤ .= Ä -X (queue iÌ Ì 4 · 0RTCCON MD { 1 a*RTCCON ^ p 2C bD 2¶ cD 0RTCALRM eD 3 s - 0RTCTIME wD 0RTCDATE D 2 D 2 ±D 4Á ¢ *PMMODE ö H 5PMADDR ¦ D 5PMDIN É D 6l Ð D 5OSCCON D D 4 v *OSCCON Q F 5SYSKEY D 6ë D 6 D 5INTSTAT D 7 "P § 5IPTMR #D 6 @D 5DMACON VD 48 c*DMACON ñ 6b dD 6× eD 7D ¸ $ 6Þ D 69 D 6Y D 5DCRCXOR D 5CHECON ðD 4á Ç*TRISG V4% û*LATG ¤ 6 D 5ETHIRQ >D 6" TD 7, io è \ 6õ D 7x 8 » 0uartReg _4 9 0RTCCON MD 1 a*RTCCON ^ 2C bD 2¶ cD 0RTCALRM eD 3 s 0RTCTIME wD 0RTCDATE D 2 D 2 ±D 4Á ¢ *PMMODE ö 5PMADDR ¦ D 5PMDIN É D 6l Ð D 5OSCCON D D 4 v *OSCCON Q 5SYSKEY D 6ë D 6 D 5INTSTAT D 7 "P § 5IPTMR #D 6 @D 5DMACON VD 48 c*DMACON ñ 6b dD 6× eD 7D ¸ $ 6Þ D 69 D 6Y D 5DCRCXOR D 5CHECON ðD 4á Ç*TRISG 4% û*LATG ¤ 6 D 5ETHIRQ >D 6" TD 7, io è 6õ D 7x 0uartReg _ì 9 ÒA ( GNU C 4.5.2 MPLAB XC32 v1.31 Compiler ETHERNET.c C:/Users/Kevin/Documents/Code/Cerebot_MX7CK_Ethernet unsigned int OI RTCOE P # HALFSEC Q # RTCSYNC R # RTCWREN S # RTCCLKON U # RTSECSEL V # SIDL X # ON Z # CAL [# ]a w ^ # Nt I __RTCCONbits_t `a g ARPT h # AMASK i # ALRMSYNC j # PIV k # CHIME l # ALRMEN m # o w p # f1 __RTCALRMbits_t r ï WAITE # WAITM # WAITB # MODE # MODE16 # INCM # IRQM # BUSY # WAITE0 # WAITE1 # WAITM0 # WAITM1 # WAITM2 # WAITM3 # WAITB0 # WAITB1 # MODE0 # MODE1 # INCM0 # INCM1 # IRQM0 # IRQM1 # 3 w # L H ï __PMMODEbits_t ¡ 3 F OSWEN G # SOSCEN H # UFRCEN I # CF J # SLPEN K # SLOCK L # ULOCK M # CLKLOCK N # NOSC O # COSC Q # PLLMULT S # PBDIV T # SOSCRDY V # FRCDIV X # PLLODIV Y # [ NOSC0 ] # NOSC1 ^ # NOSC2 _ # COSC0 a # COSC1 b # COSC2 c # PLLMULT0 e # PLLMULT1 f # PLLMULT2 g # PBDIV0 h # PBDIV1 i # FRCDIV0 k # FRCDIV1 l # FRCDIV2 m # PLLODIV0 n # PLLODIV1 o # PLLODIV2 p # r 1 w s #E J c __OSCCONbits_t u 1 VEC # SRIPL # __INTSTATbits_t !a sMCNIF t # AD1IF u # PMPIF v # CMP1IF w # CMP2IF x # U3EIF y # U3RXIF z # U3TXIF { # U2EIF | # U2RXIF } # U2TXIF ~ # I2C2BIF # I2C2SIF # I2C2MIF # FSCMIF # RTCCIF # DMA0IF # DMA1IF # DMA2IF # DMA3IF # DMA4IF # DMA5IF # DMA6IF # DMA7IF # FCEIF # USBIF # CAN1IF # CAN2IF # ETHIF # IC1EIF # IC2EIF # IC3EIF # ÙU2AEIF # U2ARXIF # U2ATXIF # U3AEIF # U3ARXIF # U3ATXIF # k SPI2EIF # SPI2RXIF ¡ # SPI2TXIF ¢ # SPI4EIF £ # SPI4RXIF ¤ # SPI4TXIF ¥ # § SPI2AEIF © # SPI2ARXIF ª # SPI2ATXIF « # SPI3AEIF ¬ # SPI3ARXIF # SPI3ATXIF ® # ° I2C4BIF ² # I2C4SIF ³ # I2C4MIF ´ # I2C5BIF µ # I2C5SIF ¶ # I2C5MIF · # ¹% I2C2ABIF » # I2C2ASIF ¼ # I2C2AMIF ½ # I2C3ABIF ¾ # I2C3ASIF ¿ # I2C3AMIF À # Â? w à #rl © MÙk % __IFS1bits_t Å? :% CNIE ; # AD1IE < # PMPIE = # CMP1IE > # CMP2IE ? # U3EIE @ # U3RXIE A # U3TXIE B # U2EIE C # U2RXIE D # U2TXIE E # I2C2BIE F # I2C2SIE G # I2C2MIE H # FSCMIE I # RTCCIE J # DMA0IE K # DMA1IE L # DMA2IE M # DMA3IE N # DMA4IE O # DMA5IE P# DMA6IE Q # DMA7IE R # FCEIE S # USBIE T # CAN1IE U # CAN2IE V # ETHIE W # IC1EIE X # IC2EIE Y # IC3EIE Z # \± U2AEIE ^ # U2ARXIE _ # U2ATXIE ` # U3AEIE a # U3ARXIE b # U3ATXIE c # eC SPI2EIE g # SPI2RXIE h # SPI2TXIE i # SPI4EIE j # SPI4RXIE k # SPI4TXIE l # nÛ SPI2AEIE p # SPI2ARXIE q # SPI2ATXIE r # SPI3AEIE s # SPI3ARXIE t # SPI3ATXIE u # wi I2C4BIE y # I2C4SIE z # I2C4MIE { # I2C5BIE | # I2C5SIE } # I2C5MIE ~ # ý I2C2ABIE # I2C2ASIE # I2C2AMIE # I2C3ABIE # I2C3ASIE # I2C3AMIE # w #9D % ± C Û i ý __IEC1bits_t ý ETHIS # ETHIP # U4IS # U4IP # U6IS # U6IP # U5IS # U5IP # U1BIS # U1BIP # U2BIS # U2BIP # U3BIS ! # U3BIP " # $ w % #² Y ý __IPC12bits_t ' X DMABUSY Z # SUSPEND [ # ON ] # _) w ` #W= È __DMACONbits_t b) {û CRCCH | # CRCTYP ~ # CRCAPP # CRCEN # PLEN # BITO # WBO # BYTO # w #z) T û __DCRCCONbits_t Ç¡ TRISB0 È # TRISB1 É # TRISB2 Ê # TRISB3 Ë # TRISB4 Ì # TRISB5 Í # TRISB6 Î # TRISB7 Ï # TRISB8 Ð # TRISB9 Ñ # TRISB10 Ò # TRISB11 Ó # TRISB12 Ô # TRISB13 Õ # TRISB14 Ö # TRISB15 × # Ù» w Ú #ÆÏ A ¡ __TRISBbits_t Ü» E TRISD0 # TRISD1 # TRISD2 # TRISD3 # TRISD4 # TRISD5 # TRISD6 # TRISD7 # TRISD8 # TRISD9 # TRISD10 # TRISD11 # TRISD12 # TRISD13 # TRISD14 # TRISD15 # ¡_ w ¢ #s å E __TRISDbits_t ¤_ ÿe TRISE0 # TRISE1 # TRISE2 # TRISE3 # TRISE4 # TRISE5 # TRISE6 # TRISE7 # TRISE8 # TRISE9 # w #þ e __TRISEbits_t +{ LATE0 , # LATE1 - # LATE2 . # LATE3 / # LATE4 0 # LATE5 1 # LATE6 2 # LATE7 3 # LATE8 4 # LATE9 5 # 7 w 8 #*© © { __LATEbits_t : W TRISF0 X # TRISF1 Y # TRISF2 Z # TRISF3 [ # TRISF4 \ # TRISF5 ] # TRISF8 _ # TRISF12 a # TRISF13 b # d¡ w e #Vµ ¾ __TRISFbits_t g¡ ³Õ TRISG0 ´ # TRISG1 µ # TRISG2 ¶ # TRISG3 · # TRISG6 ¹ # TRISG7 º # TRISG8 » # TRISG9 ¼ # TRISG12 ¾ # TRISG13 ¿ # TRISG14 À # TRISG15 Á # Ãï w Ä #² Ë Õ __TRISGbits_t Æï o¿ BUFCDEC p # MANFC r # AUTOFC t # RXEN u # TXRTS v # SIDL x # ON z # PTV { # }Ù w ~ #ní ¿ __ETHCON1bits_t Ù & RXBUF_SZ # @ w #T & __ETHCON2bits_t @ ÿn BCEN # MCEN # NOTMEEN # UCEN # RUNTEN # RUNTERREN # CRCOKEN # CRCERREN # PMMODE # NOTPM # MPEN # HTEN # w #þ l n __ETHRXFCbits_t '¾! RXOVFLWIE ( # RXBUFNAIE ) # TXABORTIE * # TXDONEIE + # RXACTIE - # PKTPENDIE . # RXDONEIE / # FWMARKIE 0 # EWMARKIE 1 # RXBUSEIE 3 # TXBUSEIE 4 # 6Ø! w 7 #&ì! ´ ¾! __ETHIENbits_t 9Ø! @÷" RXOVFLW A # RXBUFNA B # TXABORT C # TXDONE D # RXACT F # PKTPEND G # RXDONE H # FWMARK I # EWMARK J # RXBUSE L # TXBUSE M # O# w P #?%# " ÷" __ETHIRQbits_t R# Y# RXBUSY [ # TXBUSY \ # BUSY ] # BUFCNT _ # a¸# ETHBUSY c # eÒ# w f #Xë# <# # ¸# __ETHSTATbits_t hÒ# Í % RXENABLE Î # PASSALL Ï # RXPAUSE Ð # TXPAUSE Ñ # LOOPBACK Ò # RESETTFUN Ô # RESETTMCS Õ # RESETRFUN Ö # RESETRMCS × # SIMRESET Ù # SOFTRESET Ú # Ü&% w Ý #Ì:% $ % __EMAC1CFG1bits_t ß&% ÿ& FULLDPLX # LENGTHCK # HUGEFRM # DELAYCRC # CRCENABLE # PADENABLE # VLANPAD # AUTOPAD # PUREPRE # LONGPRE # NOBKOFF # BPNOBKOFF # EXCESSDFR # ¡& w #þµ& T% & __EMAC1CFG2bits_t ¡& M ' NB2BIPKTGP2 N # NB2BIPKTGP1 P # R '' w S #L ;' Ï& ' __EMAC1IPGRbits_t U '' k ' RETX l # CWINDOW n # p ¢' w q #j ¶' U' ' __EMAC1CLRTbits_t s ¢' £( SPEEDRMII ¥ # RESETRMII § # © $( w ª #¢ 8( Ð'( __EMAC1SUPPbits_t ¬ $( á ³( SCANINC â # NOPRE ã # CLKSEL ä # RESETMGMT æ # è Í( w é #à á( R( ³( __EMAC1MCFGbits_t ë Í( +) READ # SCAN # E) w #Y) û( +) __EMAC1MCMDbits_tE) q Æ) À r # SCAN s # t # u # w à) w x #p ô) s) Æ) __EMAC1MINDbits_t z à) ~ a* À # SCAN # # # {* w #} * * a* __EMACxMINDbits_t {* long unsigned int long int int char short unsigned int short int signed char long long int UINT T unsigned char long long unsigned int N+ reg P+ # clr Q+ # set R+ # inv S+ # + REG_SET TS+ PVö+ mode Xö+ # sta Yö+ # tx Zö+ # rx [ö+ #0 brg \ö+ #@ + UART_REGS ]¨+ __uint8_t /(+ __uint16_t 1Ù* __uint32_t 3 °, BYTE_0 , # BYTE_1 ! , # BYTE_2 " , # BYTE_3 # , # BYTE_4 $ , # BYTE_5 % , # Ë, A, bytes 'Ë, , Û, ©* ETH_MAC_ADDRESS (°, +. w - # COLLISION_COUNT . # î / # o 0# Ú 1 # DONE 2 # MULTICASE 3 # Z 4 # PACKET_DEFER 5 # EXCESSIVE_DEFER 6 # MAXIMUM_COLLISION 7 # LATE_COLLISION 8 # GIANT 9 # UNDERRUN : # BYTES_TRANSMITTED < # = #Æ > #BACKPRESSURE ? #º @ # *¶. ò, O C¶. /, Æ. ©* ETH_TRANSMIT_STATUS_VECTOR D. GQ1 w I # LONG_DROP_EVENT J # RXDV_EVENT K # CARRIER_EVENT L # CODE_VIOLATION M # î N # o O# Ú P # RECEIVE_OK Q # MULTICAST R # Z S # DRIBBLE_NIBBLE T # U # Æ V # UNKNOWN_OP_CODE W # º X # PKT_CHECKSUM [ #RUNT_PACKET ] #BROADCAST_OR_NOT_DEST ^ #HASH_TABLE_MATCH _ #MAGIC_PACKET_MATCH ` #PATTERN_MATCH a #UNICAST_MATCH b #BROADCAST_MATCH c #MULTICAST_MATCH d # Fj1 è. O f¶. ETH_RECEIVE_STATUS_VECTOR gQ1 i2 EOWN k # NPV l # w n # EOP p # SOP q #r/, # TSV sÆ. # ETH_TX_ETHERNET_DESCRIPTOR t1 v£2 EOWN x # NPV y # w { # EOP } # SOP ~ #/, # RSV j1 # ETH_RX_ETHERNET_DESCRIPTOR (2 $î2 £ î2 # next_ED /, # 2 þ2 ©* ETH_TX_DESCRIPTOR_TABLE Å2 $F3 £ F3 # next_ED /, # £2 V3 ©* ETH_RX_DESCRIPTOR_TABLE 3 64 TX_ED_table þ2 # RX_ED_table V3 #$ TX_ED_buffer 64 #H RX_ED_buffer 64 #¨ TX_descriptor_index , #@ RX_descriptor_index , #@c O4 #@Í O4 #@ , M4 ©* ©* ï M4 ETH_DATA u3 VA_TO_PA /, 4 n¢4 ptr /, ret /, ETH_Init 4 ´ n25 data 25 ( c O4 , Í O4 0 Delay_US Ê* 5 i + , value n , Delay_MS vÊ* U4 ETH_PHY_Read È , ´ P n}5 address È , reg È , ETH_PHY_Write ÑP Ì nÏ5 address Ñ , reg Ñ , value Ñ , !ETH_Recv_Queue Ø , Ì ø nETH_Read_Packet Ý , ø T np6 buffer Ýp6 length Ýv6 i Þ , j Þ , size ß , "ã à , , , #ETH_Write_Packet , T ¨ n27 $dest Û, $src Û, $length , $buffer p6 ,%i , %write_index , %read_index , &ã , '__ETH_Interrupt_Handler 1¨ np7 %value 2/, (RTCCON M7 )O a*RTCCON 7 t *E b7 * c7 (RTCALRM e7 +ô s! Û7 1 (RTCTIME w7 (RTCDATE 7 *ç 7 ** ±7 ,Í ¢ *PMMODE 28 L -PMADDR ¦ 7 -PMDIN É 7 -OSCCON D 7 , v *OSCCON 8 J -SYSKEY 7 .# 7 .¸ 7 -INTSTAT 7 / "- Õ8 -IPTMR #7 ,t Æ*IFS1 þ8 l ,< *IEC1 9 D , (*IPC12 19 ² .d @7 -DMACON V7 ,Ø c*DMACON k9 = .8 d7 . e7 / ± 9 ) .¥ 7 .l 7 .Ä 7 -DCRCXOR 7 -CHECON ð7 ,n Ý*TRISB : Ï , ¥*TRISD : s ,° *TRISE 9: ,É ;*LATE R: © , h*TRISF l: µ , Ç*TRISG :/] Z : í . 7 / c Â: T -ETHTXST 7 -ETHRXST ¡7 /ø 3 ý: ,Ò :*ETHIEN ; ì! . ;7 -ETHIRQ >7 , S*ETHIRQ R; %# .P T7 /x i! w; ë# /ð à ; :% /* ¥; µ& .¶ 1 7 /A V Ê; ;' /B t á; ¶' .Y 7 /Ù 6 < 8( /¨ ì ¦ < á( /þ i 4< Y) .º 7 .® 7 .8 ; 7 . U 7 / { } < ô) /*  < * .B 7 .K « 7 .T Ç 7 Ô< Ô< 0 û+ (uartReg _ë< 1É< eth_data 25 (RTCCON M7 )O a*RTCCON 7 *E b7 * c7 (RTCALRM e7 +ô s! Û7 (RTCTIME w7 (RTCDATE 7 *ç 7 ** ±7 ,Í ¢ *PMMODE 28 -PMADDR ¦ 7 -PMDIN É 7 -OSCCON D 7 , v *OSCCON 8 -SYSKEY 7 .# 7 .¸ 7 -INTSTAT 7 / "- Õ8 -IPTMR #7 ,t Æ*IFS1 þ8 ,< *IEC19 , (*IPC12 19 .d @7 -DMACON V7 ,Ø c*DMACON k9 .8 d7 . e7 / ± 9 .¥ 7 .l 7 .Ä 7 -DCRCXOR 7 -CHECON ð7 ,n Ý*TRISB : , ¥*TRISD : ,° *TRISE 9: ,É ;*LATE R: , h*TRISF l: , Ç*TRISG : /] Z : . 7 / c Â: -ETHTXST 7 -ETHRXST ¡7 /ø 3 ý: ,Ò :*ETHIEN ; . ;7 -ETHIRQ >7 , S*ETHIRQ R; .P T7 /x i! w; /ð à ; /* ¥; .¶ 1 7 /A V Ê; /B t á; .Y 7 /Ù 6 < /¨ ì ¦ < /þ i 4< .º 7 .® 7 .8 ; 7 . U 7 / { } < /*  < .B 7 .K « 7 .T Ç 7 (uartReg _ÐA 1É< ¦ GNU C 4.5.2 MPLAB XC32 Compiler v1.20 /home/plibbuild/work/pic32-plib/peripheral/timer/source/read_core_timer_lib.c ReadCoreTimer >ä ì m »5 GNU C 4.5.2 MPLAB XC32 Compiler v1.20 /home/plibbuild/work/pic32-plib/peripheral/pcache/source/pcache.c CheKseg0CacheOff 5 ¤ mCheKseg0CacheOn L¤ ¼ m ® Z GNU C 4.5.2 MPLAB XC32 Compiler v1.20 /home/plibbuild/work/pic32-plib/peripheral/int/source/int_configure_system_lib.c ( INTConfigureSystem 7 @ m ° GNU C 4.5.2 MPLAB XC32 Compiler v1.20 /home/plibbuild/work/pic32-plib/peripheral/int/source/int_enable_interrupts_lib.c 8 INTEnableInterrupts 3ì ô m ² ¤ GNU C 4.5.2 MPLAB XC32 Compiler v1.20 /home/plibbuild/work/pic32-plib/peripheral/int/source/int_disable_interrupts_lib.c H INTDisableInterrupts 3ô ü m ² É GNU C 4.5.2 MPLAB XC32 Compiler v1.20 /home/plibbuild/work/pic32-plib/peripheral/int/source/int_restore_interrupts_lib.c X INTRestoreInterrupts 3p m Ú î GNU C 4.5.2 MPLAB XC32 Compiler v1.30 /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs/default-bootstrap-exception-handler.c _bootstrap_exception_handler / Ø m ´ GNU C 4.5.2 MPLAB XC32 Compiler v1.30 /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs/default-on-reset.c _on_reset )ü m ¼ 4 GNU C 4.5.2 MPLAB XC32 Compiler v1.30 /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs/default-on-bootstrap.c _on_bootstrap ) m Ö W GNU C 4.5.2 MPLAB XC32 Compiler v1.30 /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs/default-general-exception-handler.c _general_exception_handler -Ø m Î z GNU C 4.5.2 MPLAB XC32 Compiler v1.30 /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/default_vector_dispatch/defaultinterrupt.c _DefaultInterrupt 0@ p m % $ > : ; : ; I 8: ; I : ; I : ; : ;I 8: ; : ;I : ; ( : ; I85 I : ; I I ! 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I/ ' I .? : ; ' I@: ; I4 : ; I.? : ; ' @: ; I.? : ; I< .? : ; I< !. ? : ; ' I@"4 : ; I#.? : ;' I@$ : ;I%4 : ;I&4 : ;I'.? : ;' @(4 : ; I? < )4 : ; @I? < *4 : ; I? < +4 : ; @I? < ,4 : ;@I? < -4 : ;I? < .4 : ;I? < /4 : ;@I? < 0! 1& I % RU . ? : ; @% RU . ? : ; @% RU . ? : ; @% RU . ? : ; @% RU . ? : ; @% RU . ? : ; @% . ? : ; @% . ? : ; @% . ? : ; @% . ? : ; @% . ? : ; @ Ü û c:/users/kevin/documents/code/cerebot_mx7ck_ethernet c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include/peripheral c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include/proc c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include/machine main.c system.h osc.h dma_5xx_6xx_7xx.h p32mx795f512l.h generictypedefs.h uart.h int_types.h ethernet.h int.h (?,»(v?=»(vò8¬v@5º¯ºæ»>ÌxJ,»»ó»¼Ätcºæ»> b<ÔxJHºÛ JP¾»9z»»¾(JL¼½»»» ~º½Àóóóóóóóöv ((((0F»»> $ û c:/users/kevin/documents/code/cerebot_mx7ck_ethernet c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include/proc c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include/peripheral c:/program files (x86)/microchip/xc32/v1.31/pic32mx/include/machine ethernet.c p32mx795f512l.h generictypedefs.h uart.h int_types.h ethernet.h ó»K>$»½óó»> ó=óóó====>¼¯¯xD¬¼ç$xH ¬=Cu¯êóóóóóóuó½=ô==ó=y@>=?¾?õ===óó===óå=?ó½å¯õ====½»»¾óóóóóóó=óóô>ó>>=>>=>==>æ=»uó»ôå»»uô»»??½»(ã¼ã½(»»8$åå$0>½j,¬K?$KK½ó½==ååæ»4¸°»4¸°40½0»4»·ëu=v4K>»>ô>÷=óóô=óóô>ô?ô?õó j d û /home/plibbuild/work/pic32-plib/peripheral/timer/source read_core_timer_lib.c ^ X û /home/plibbuild/work/pic32-plib/peripheral/pcache/source pcache.c m g û /home/plibbuild/work/pic32-plib/peripheral/int/source int_configure_system_lib.c n h û /home/plibbuild/work/pic32-plib/peripheral/int/source int_enable_interrupts_lib.c o i û /home/plibbuild/work/pic32-plib/peripheral/int/source int_disable_interrupts_lib.c o i û /home/plibbuild/work/pic32-plib/peripheral/int/source int_restore_interrupts_lib.c û /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs default-bootstrap-exception-handler.c z û /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs default-on-reset.c ~ û /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs default-on-bootstrap.c û /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/stubs default-general-exception-handler.c û /Volumes/home/c11067/xc32/build/xc32-XC32_v1_30_branch/pic32-libs/libpic32/default_vector_dispatch defaultinterrupt.c ÿÿÿÿ | D HD t D HD DÈXHD ÿÿÿÿ | d 4 DDD d 4 D(PD d ´ DDD d P | DDD d Ì , DDD d ø \ DDD d T T DDD @ d ¨ ` Px` T @A ÿÿÿÿ | ä ÿÿÿÿ | ¤ ÿÿÿÿ | Ð 0 ÿÿÿÿ | ð ì ÿÿÿÿ | ô ÿÿÿÿ | 0 p ÿÿÿÿ | P 8 HD ÿÿÿÿ | x ü ÿÿÿÿ | ÿÿÿÿ | ¸ Ø 8 HD ÿÿÿÿ | à @ 0 *EMACxMIND RTCCONbits RTCALRMbits ETHIRQCLR ETHSTATbits DMACONbits RTCCONCLR BUFFER_ADDR VLAN_TAGGED registers *ETHSTAT EMACxMINDbits ALRMTIME INTCONSET LENGTH_CHECK_ERROR BROADCAST RTCCONSET CRC_ERROR LENGTH_OUT_OF_RANGE DCRCCONCLR pb_clock PAUSE_CONTROL_FRAME ALRMDATE BMXCONCLR INTSTATbits LATGbits int_status DCRCCONSET DCRCCONbits *INTSTAT DCRCDATA DMACONCLR AD1PCFGSET CONTROL_FRAME ETHCON1SET startTime *RTCALRM sys_clock OSCCONbits *DCRCCON PMMODEbits BYTE_COUNT DMACONSET TRISGbits INTCONCLR EMACxMCMD descriptor BUFFER_ADDR ETHIENCLR TRISGbits EMACxMINDbits DMACONCLR EMAC1SA0 EMAC1SA1 EMAC1SA2 ETHCON1bits *EMAC1MCMD IFS1bits *EMAC1MIND ETHCON1SET TRISDbits LINKFAIL *EMAC1MCFG *DCRCCON EMACxMCMD DCRCDATA rx_callback EMAC1SUPPbits ALRMTIME EMAC1CFG1bits EMAC1MCMDbits DMACONSET *EMAC1CLRT *ETHSTAT ALRMDATE *ETHRXFC IEC1bits RTCCONCLR registers EMAC1MAXF tx_callback LENGTH_CHECK_ERROR TRISFbits *EMAC1IPGR EMAC1MINDbits DCRCCONCLR TRISEbits VLAN_TAGGED PAUSE_CONTROL_FRAME LENGTH_OUT_OF_RANGE CRC_ERROR ETHRXFCbits NOTVALID DCRCCONbits RTCCONSET INTCONCLR *INTSTAT *EMAC1SUPP EMAC1IPGRbits RTCCONbits *ETHCON1 *ETHCON2 DCRCCONSET BYTE_COUNT EMAC1MRDD ETHIRQbits ETHCON2bits descriptor EMAC1MADR INTCONSET *EMACxMIND PMMODEbits DMACONbits descriptor_index RTCALRMbits OSCCONbits *EMAC1CFG1 *EMAC1CFG2 *RTCALRM EMAC1CFG2bits EMAC1MWTD EMAC1CLRTbits ETHIRQCLR BROADCAST BMXCONCLR TRISBbits ETHSTATbits INTSTATbits IPC12bits CONTROL_FRAME EMAC1MCFGbits EMAC1IPGT MIIMBUSY LATEbits ETHIENbits ÷ ò p __RTCCONbits_t - __RTCALRMbits_t H __PMMODEbits_t F __OSCCONbits_t __INTSTATbits_t __DMACONbits_t __DCRCCONbits_t V__TRISGbits_t __LATGbits_t \ __ETHSTATbits_t __EMACxMINDbits_t Ü UINT Y REG_SET » UART_REGS Ì __uint8_t Ý __uint32_t ETH_MAC_ADDRESS t ETH_TRANSMIT_STATUS_VECTOR ETH_RECEIVE_STATUS_VECTOR ´ ETH_TX_ETHERNET_DESCRIPTOR Q ETH_RX_ETHERNET_DESCRIPTOR ¬ ETH_TX_DESCRIPTOR_TABLE ETH_RX_DESCRIPTOR_TABLE ETH_DATA ò ÖA t __RTCCONbits_t 1 __RTCALRMbits_t L __PMMODEbits_t J __OSCCONbits_t __INTSTATbits_t l __IFS1bits_t D __IEC1bits_t ² __IPC12bits_t = __DMACONbits_t ) __DCRCCONbits_t Ï __TRISBbits_t s __TRISDbits_t __TRISEbits_t © __LATEbits_t µ __TRISFbits_t __TRISGbits_t í __ETHCON1bits_t T __ETHCON2bits_t __ETHRXFCbits_t ì! __ETHIENbits_t %# __ETHIRQbits_t ë# __ETHSTATbits_t :% __EMAC1CFG1bits_t µ& __EMAC1CFG2bits_t ;' __EMAC1IPGRbits_t ¶' __EMAC1CLRTbits_t 8( __EMAC1SUPPbits_t á( __EMAC1MCFGbits_t Y) __EMAC1MCMDbits_t ô) __EMAC1MINDbits_t * __EMACxMINDbits_t + UINT + REG_SET û+ UART_REGS , __uint8_t , __uint16_t /, __uint32_t Û, ETH_MAC_ADDRESS Æ. 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C1FIFOINT15CLR U1TOKSET AD1CHSINV _ramfunc_begin I2C3AMSK U1BRG C2FIFOINT2SET DCH5INTSET CNENCLR C1FIFOCI31CLR I2C5MSKSET I2C3CONCLR CM2CONINV U6MODECLR C1FIFOCI31 TRISBINV ODCBSET U6STASET I2C4BRG RCONSET C2FIFOINT11INV C1FIFOCI16SET C1FIFOCI31INV IFS2INV ODCDCLR IEC1CLR C2FIFOCI25INV _sdata_end AD1CON1SET EMAC1CFG1 DCH6DSAINV C2FIFOCON11SET LATCCLR U5STAINV C1FIFOINT3INV C2FIFOUA28SET SPI1STAT I2C2CONINV I2C1AADDSET DCH5SSACLR C2FIFOUA16CLR ETHMCOLFRMINV EMACxMADRCLR DMASTATINV C2RXF3INV C1FIFOUA4CLR U3BSTA I2C2AADDSET C1FIFOCI0 SPI3CON DCH2CSIZ C2FIFOCI22SET C2RXF25SET I2C5STATCLR AD1PCFGSET C1TMRCLR C2FSTATCLR C2FIFOUA26 C2FIFOUA24SET C2FIFOCI16INV DCH4DPTRCLR OC4RS C2FIFOUA25 C1FIFOCI1 C1FIFOCI12SET U1BRGCLR DCH4SPTRINV U3ASTACLR U5BRGSET ETH_Recv_Queue _ebase_address C1FIFOCI3 AD1CSSL I2C1ABRGSET PORTBSET C1FIFOCI23SET C1RXF5SET C1RXF12CLR IPC1CLR DCH1CPTRINV U2BBRGINV C1FIFOCI27SET I2C2AMSKINV C2FIFOUA3INV C1FIFOCI2 C2TREC C2FIFOUA22 C1FIFOCON15SET CMSTATINV C2FIFOCI21CLR C1FIFOUA29INV C2FIFOUA21 DCH0CPTRINV C1FIFOCON21SET DCH7CON C2RXF7SET C1FIFOCI4 CheKseg0CacheOn C1FIFOINT8CLR ETHSCOLFRM C1RXF14INV _DDPSTAT C2RXF14SET ODCECLR C2FIFOCON10INV C2FIFOCON10CLR NVMDATA EMAC1IPGT EMACxMADRINV RTCTIMECLR ODCACLR C2FIFOUA23 C1FIFOCON15 DCH2CON OC5RSSET C1FIFOCI20INV C2FIFOUA24 C1CFGINV SPI3ABRGSET U5MODECLR C1FIFOCI20CLR C1FIFOCON8INV _APPOSET C1FIFOINT9SET C2INTINV C2FIFOINT14SET DCH2CPTR C1FIFOUA8CLR C1FIFOCON26SET C2FIFOINT22SET U1EP10 TMR5INV EMACxMCMD C2FIFOCI12CLR EMAC1IPGR DCH2SSA U2BRG C1FIFOCON18 C1FIFOUA16INV __vector_dispatch_48 U1BRGINV OSCTUNSET C2FIFOINT0CLR C2FIFOUA1CLR BMXPUPBASET C2FIFOCI9CLR C1FIFOUA6INV C1FIFOUA6SET __vector_dispatch_49 PR1CLR DCH2CONCLR C1FIFOCON17 C2FIFOCON24SET C1FIFOCON16 SPI1BRGINV DCH1SSIZ DCH3CSIZINV C1FIFOCON30INV I2C2STATSET DCH6SSA C2FIFOCON20CLR C2FIFOCON24CLR OC4RSSET IPC3INV C1RXF18 C1RXF19 IEC1INV C2FIFOCON0SET C2FIFOINT19CLR C1FIFOCON10SET C2FIFOCON12CLR C2RXF16CLR SPI2ACON DCH0CSIZCLR DCH3SSIZSET C1RXF16 I2C3ASTATINV C1RXF15 C1TMR U3BBRG DCH0DATSET C1RXF17 C1FIFOUA21CLR EMAC1MRDDSET U3ASTA ODCCINV C2FIFOBA C1RXF13 C2FIFOCON7INV C2FIFOCON16CLR NVMADDRCLR C1RXF12 AD1CON1CLR DCH2CPTRSET __vector_dispatch_43 C1RXF14 C2FIFOCON29INV _STROCLR __vector_dispatch_42 C1FIFOCON7CLR C2FIFOINT11SET C1FIFOUA2 I2C3BRGINV AD1CSSLCLR C2FLTCON0CLR PORTCINV C2RXF13INV __vector_dispatch_47 C1FIFOCON10CLR SPI2ABRGSET DCH3CPTRINV C1RXM0SET __vector_dispatch_41 _bootstrap_exception_handler ETHCON2CLR DCH4CONSET C1FIFOUA4 __vector_dispatch_46 C1FIFOUA0 LATESET C2FIFOINT7SET U1ARXREG C1FIFOINT24INV EMAC1TESTCLR T4CONSET __vector_dispatch_45 __vector_dispatch_40 DCH3DATCLR C1FIFOUA30CLR C1FIFOUA14INV DCH0DPTRCLR ODCFCLR I2C5CONCLR EMAC1SA1INV C1FIFOUA3 C2RXM1INV DCH1CPTR __vector_dispatch_44 IC5CON DCH3DSASET T2CONSET RTCCONCLR T3CONSET C1FIFOCI9INV DCH1CSIZINV C1FIFOUA7 DCH4SSIZCLR U1BSTASET DCH7INTSET SPI4STATINV C1CONINV C2FIFOUA7INV C1FIFOUA6 RCONINV DCH6CONSET C2RXF24INV U3STAINV C1FIFOUA5 C1FIFOUA1INV I2C1ADDSET IPC3CLR DCH1SSAINV EMAC1CFG2 I2C1CONINV memset C2FIFOCON0CLR C1FIFOUA19CLR ETHIRQSET C1RXF12INV EMACxCLRTCLR C2FIFOCON12SET C2FIFOINT22 DCH5DATINV C2FIFOINT27SET C1FIFOCON19CLR C2RXF18CLR EMACxMWTDINV C2FIFOCI18CLR DCH7SPTRSET OSCCON C2RXF12INV CVRCONSET C1RXF8SET C2FIFOINT20 U1EP5SET IPTMRSET DCH2DPTR C1TRECINV C2TRECCLR C1FIFOCON7SET C1FIFOUA1 C2FIFOCI3SET C2FIFOINT21 IPC5CLR DCH1DSIZCLR C2FIFOUA9CLR C2FIFOCI27CLR C1FSTATSET DCH4SSIZSET AD1CON2SET PORTDCLR C2FIFOINT23 C1FSTATCLR U1EP0CLR C2FIFOINT9SET C1FIFOCI19INV PMDOUTSET U1CNFG1CLR C2FIFOINT16SET C1FIFOCON19 C1FIFOUA0CLR U3BRG IPC2SET U4STACLR DCH1DATCLR C2FIFOINT25 OC2RSET U3AMODESET ETHRXOVFLOWCLR CHECONSET I2C5STATSET ETHIENCLR C2FIFOCON31CLR C2FIFOINT6INV DEVCFG0 U1BBRG C1VECSET C2FIFOUA27CLR I2C2ABRGINV C2FIFOCON17CLR DEVCFG1 C2FIFOINT26 C2FIFOCON3SET EMAC1MCFG C2RXM2SET I2C2ADDSET CNCONSET EMAC1MADRCLR ETHCON2INV U2ABRG DCH3DATSET C2FIFOINT24 C2FIFOINT16CLR LATFSET C1FIFOUA27INV C1FIFOINT7CLR C1FIFOCI3SET DCH3INTINV C1FIFOCON0INV U1EP2INV U3ATXREG DCH2CSIZSET I2C1CON C2RXF4INV C1INT C2FIFOINT5INV C2FIFOINT27 C2FIFOCON19CLR C2FIFOCI12INV U1EP10CLR SPI4BRGINV CHEMSKCLR C2FIFOUA20INV C2FIFOCI5SET IC3BUF C1FIFOINT10SET CHEACC C2FIFOINT28 DEVCFG2 C1RXF30INV C1FIFOCI29INV I2C2ADD OC5RS RTCCON ODCCCLR C1RXF6INV C2FIFOINT11CLR AD1PCFGINV NVMADDRINV U1BDTP2SET LATACLR EMAC1SA0INV C2FIFOCI10CLR C1FIFOCI18SET C1FIFOCON5CLR C2FIFOCI15INV C1FIFOCON31INV IPC8SET ALRMDATECLR I2C2ABRGCLR EMACxMCMDCLR C1CONCLR DCH6ECONSET ETHPMCS C2RXOVFCLR TMR4INV C2FIFOINT29 I2C5MSKCLR PR3CLR C2FIFOUA31INV DEVCFG3 SPI1ABRG SPI3ASTAT C1FIFOCON4SET IC1CON EMAC1MINDINV I2C1ATRNCLR SPI2ASTATSET C1RXOVFINV C1RXF5INV C1FIFOCON18INV _vector_spacing RTCALRMINV DCH7DPTR DCH6DATCLR C2FIFOINT29INV DCH4DSACLR C2RXM0CLR C2FLTCON4CLR C1FIFOUA23 EMAC1SUPPCLR IPC12SET IPC6INV C1FIFOUA24CLR CNENINV C2RXF5INV ETHFRMRXOKCLR C1FIFOUA22 C2FIFOINT27CLR U2ARXREG C2FIFOCI14SET DCH7CONCLR C1FIFOUA20INV PMDIN I2C3ATRNINV DCH2INT C2FIFOCI21INV C1FIFOCI18INV U3ABRGCLR DCH6CSIZSET C2FIFOUA7SET C2FIFOCON7SET C2FIFOCI24INV C2FIFOUA21SET BMXDRMSZ C2FIFOINT22CLR RTCDATECLR U1OTGIE C2FIFOUA10SET U3BMODE C2FIFOCI31CLR C2FIFOCON23CLR DCH7DSIZINV C1FIFOCI9CLR C1FIFOCI1SET ETHFCSERRINV C1FIFOCI29SET IPC1INV C1FIFOINT21SET C1RXF23INV C1FIFOUA20 _reset C2FIFOCON22CLR ETHFRMTXOK C1FIFOUA21 C1FIFOINT11INV U5STA C1FIFOUA11CLR U1MODEINV ETHIEN DCH2DPTRSETU1EP7SET U1OTGIR PMADDRSET SPI4STATCLR EMAC1MWTDCLR T5CON IPC6CLR LATEINV SPI3STAT ODCGSET ETHRXFCSET C1FIFOCI31SET DCH0DSASET C1FIFOUA31CLR SPI2ABRGCLR DCH2DAT DCH4CSIZ OC5CON C1FLTCON0INV C2FIFOINT17CLR I2C3ADDSET ODCCSET OSCTUNCLR C1FIFOCI28CLR C2FIFOCON15INV PMMODEINV U2BMODEINV C1FIFOUA3CLR CNCONINV DCH1DPTR _heap I2C1ACONCLR SPI3ASTATINV IC2CONSET _DefaultInterrupt C2FIFOINT18INV U1BDTP1CLR C1FIFOCI17CLR C1FIFOCON31CLR DCH7CSIZ ETHRXSTINV SPI2BRGSET _DBG_CODE_ADDR CNCON OC3CONSET DCH6CPTRINV PORTECLR U1EP11SET PORTBINV LATCSET C1VEC C2FIFOCON18INV U1PWRC C1FIFOINT6CLR C2FIFOINT0SET C1FIFOCON19SET I2C3ACONSET C2FIFOINT24CLR C2FLTCON3CLR C1RXF30CLR DCH1SPTRINV C1FIFOCI26INV DCH0CON IFS1INV DCH1CPTRSET I2C3AADDSET TRISFINV C1FIFOUA22CLR C1FIFOINT19SET _APPOINV EMACxCFG2CLR U1EP12CLR C2FIFOCON29CLR DCH4CPTR C1FIFOCI15INV C1FIFOINT10 C1FIFOBA C1FIFOUA9CLR U2BSTASET U3ARXREG IC3CON _APPOCLR I2C2AADDINV DCH7DSIZSET ETHPMCSSET PORTFCLR C2FLTCON4SET U1BMODEINV DCH4SSASET C2RXF9INV U2BBRGCLR C1RXF4CLR C2FIFOCI23SET DCH5DATCLR IC4CONSET U1TXREG C1FIFOCI20SET PR5SET C2INT SPI1ACONSET C2RXF9CLR U2AMODESET C1FIFOINT14 C2FIFOUA12INV DCH1DPTRCLR DCH3SSA DCH6DSACLR C1FIFOINT11 C1FIFOCON4INV I2C3STATINV DCH5CON C1FIFOINT25CLR C2FIFOUA7CLR C2FIFOUA0SET DCH3SSAINV I2C1AMSKCLR RTCTIMEINV C1FIFOINT13 C2INTCLR _bmxdudba_address EMACxIPGTINV ETHFCSERRCLR C1FIFOINT15 U4TXREG C2RXF20INV I2C3ADDINV U3AMODE ETHMCOLFRMCLR C2FIFOUA2SET C1FIFOINT18 C2RXF10INV C2FIFOINT13SET C1FIFOCON12CLR C1FIFOINT16 C2FIFOCI24CLR DCH3DSIZSET SPI3ASTATCLR IPC10 C1FIFOUA9SET IC1BUF C1FIFOINT14INV I2C2TRNSET C2FIFOUA19INV I2C4STATCLR C1FIFOINT12 C2FIFOCI22CLR DCH7DATCLR SPI1ABRGSET SPI3BRGCLR _eheap DMACONSET C1FLTCON7INV PORTESET EMAC1TESTINV C1FIFOCON0SET C1FIFOCI22INV CMSTATCLR I2C2ASTATCLR U1EIR C1FIFOCON31SET I2C1ATRNINV I2C4STATSET C1FIFOINT17 SPI2CONCLR C1FIFOCON22SET I2C4MSK C1FIFOCI6 PMDINCLR DCH4SPTRCLR U1IE I2C1ATRN U1BDTP2CLR C2FIFOCI15CLR DCH6CONINV C1TRECSET I2C1ACON U1IR I2C1CONCLR ETHPMM1SET C1FIFOCI9 C2FIFOINT13CLR C1FIFOCI5 C2FIFOCI13CLR ETHFRMTXOKCLR C1FIFOINT19 I2C4STAT DMASTAT DCH7ECONINV C1FIFOCON2INV C1FIFOCI11INV C1FIFOCI8 I2C3AADDINV PR5INV U1EP0INV U1EIESET DCH3INT OC1R DCH3CSIZ C2RXOVFINV DCH7CPTRINV C2FIFOUA27 _init DCH3SSACLR C2FIFOINT8SET SPI2BRGINV C2FIFOINT6CLR C1FIFOCI7 LATECLR C1RXOVF C2FIFOUA28 U2BMODECLR C2FIFOINT28CLR DCH5CONINV C1FIFOINT8SET C1FIFOCON6INV EMAC1SA2CLR PR3INV DCH3SPTRINV _DBG_EXCPT_ADDR I2C4BRGINV DCH4DPTR C1FIFOINT11CLR DCH2DSIZINV C1FIFOUA1CLR U1EP10INV DCH6SPTRINV DCRCXOR DCH2SSACLR C1FIFOINT25INV OC1RCLR U1SOFSET C1FIFOCON11SET C2FIFOUA13CLR DCH1ECON ADC1BUF9 PMSTATCLR OC5RSCLR C2FIFOCON17INV U1CON U3BRGCLR C1FIFOINT22INV ADC1BUF8 C2FIFOCI29CLR EMACxMWTD U1EP15CLR C2FIFOUA29 DCH7SSIZ C2FIFOUA23INV DCH5DPTRINV ETHPMM0SET C2RXM0 EMAC1SA1SET EMAC1MADRINV C2FIFOCON8CLR EMAC1MINDCLR C1FLTCON4INV C1FIFOCON1 C2FIFOINT24SET IFS2CLR U1EP15SET OC2CONSET C2RXM1 U1SOFINV C1FIFOCI19SET C2RXM1SET I2C2MSK C1FIFOCON16INV C1FIFOCON2 C2FIFOCON10 C1FLTCON2SET C2FIFOUA14CLR C2FIFOUA30 C2FIFOCI0INV OC5CONSET CHEACCSET C2FIFOUA26CLR C1FIFOUA17CLR IPC4INV ETHRXOVFLOWINV DCRCCONSET BMXBOOTSZ C1VECCLR C2FIFOUA31 DCH0CONCLR I2C3ABRGINV U1EP8CLR U4STA U1BDTP3INV _BEV_EXCPT_ADDR SPI2ACONINV IPC8INV C2FIFOCON4SET SPI2BUF EMACxSA1SET C2FIFOUA5CLR C1FIFOCON3 C1FIFOINT14CLR U1CNFG1SET DCH6CSIZINV C2FIFOCON14 C2FIFOUA6CLR _nmi_handler C2RXF20CLR C2FIFOCON11 C2FIFOINT16INV C1FIFOCON0 C1FIFOCON4 DCH6DPTRSET I2C3AMSKCLR C1FIFOINT7INV I2C3BRG C2FIFOUA8CLR C1RXF21INV AD1PCFGCLR OC1CONINV C2RXM2 SYSKEYSET C1FIFOUA20CLR C2RXM3 C2RXF30 C2FIFOCON13 EMACxCLRT SPI4BRGSET EMACxMADRSET DCH7CONSET I2C1ADDCLR TRISASET C1RXF10INV DCH3SSIZINV C2RXF31 U2ABRGINV DCH3DATINV RTCCONINV DCH5SPTRSET ETHSTATSET OC5R C2FIFOCON15 IFS0INV C2FIFOINT19INV C2RXF22INV C1FIFOINT1SET I2C3BRGSET OC2RCLR U1BBRGINV C1FIFOINT16INV EMAC1CLRTSET C1FIFOINT30SET C1FIFOINT6INV C2FIFOCON18 C2FIFOCON19INV U1BDTP3CLR RTCTIME __crt0_exit DCH4CON RCON I2C2ADDINV U2AMODEINV DCH3DSIZINV C2FIFOCON12 C2FIFOCON16 U1EP6SET C1FIFOINT4 SPI2CON IPC9INV PORTDINV AD1CON3CLR I2C3CONSET EMACxMWTDCLR I2C5ADDCLR I2C3MSKCLR EMAC1MAXFSET U6BRGINV LATASET ADC1BUF1 C1FIFOINT31INV I2C4TRN C2FIFOINT29CLR C2RXF3CLR C1FIFOINT3 ADC1BUF0 C2FIFOCON15CLR U1EP12INV ODCA EMACxIPGT DCH6INTSET C2FIFOCI19CLR C1FIFOINT14SET I2C3ATRNCLR ADC1BUF3 ODCB OSCCONINV C1FIFOINT0 ETHRXSTCLR C2FIFOUA21INV I2C2ATRNINV ETHIENINV ADC1BUF2 EMACxIPGR ODCE EMACxMCMDSET SPI4BRG ADC1BUF5 EMACxCFG1CLR C1FIFOINT1 C2FIFOCON17 OSCTUNINV ODCF C1FIFOCI7SET ETHRXST I2C2ASTATSET C2FIFOUA3SET DCH1DATSET ADC1BUF4 C2FIFOCON19 ODCC C2FIFOUA24CLR ETHSTATCLR C1FIFOCI4SET ADC1BUF7 C2FIFOUA10INV CM2CON I2C3ABRGCLR ODCD DCH4DATSET C2FLTCON2INV C2FIFOCON21INV DCH7DPTRCLR U6MODESET C2FIFOCON18CLR BMXDKPBA ADC1BUF6 C1FIFOINT2 I2C1ASTATCLR C2FLTCON6CLR EMAC1IPGRSET I2C1STATINV TRISGINV C2FIFOCI28CLR C1FLTCON7SET PMMODECLR CHEACCCLR C1FIFOUA24INV I2C2ATRNSET C2RXF7CLR C1FIFOCON29SET DCH1SSA DCH0CSIZSET DMASTATCLR C2FIFOINT27INV U1ABRGCLR DCH5CSIZ __MIN_HEAP_SIZE SPI3ABUF EMAC1SA1CLR OC3RCLR U1EP9CLR C1FIFOCI17SET U1ABRGINV ETHPMO C2FIFOCON9SET C1FIFOCI25INV C2FIFOCON26SET I2C3TRNINV DCH3DPTR U1EP11INV U1EP7INV DCH7INTCLR ODCESET DCH5DSIZCLR ETHRXWMCLR OC1CONSET DCH1CONINV C1FLTCON4SET EMAC1CFG1SET DCH1CSIZSET DCH0INTINV BMXDUDBA C1FIFOUA11INV C2FIFOCI9SET I2C3TRN C1FIFOCON9 U2BSTAINV C1FIFOINT22CLR C2RXF21SET C2FLTCON3INV C1FIFOINT25SET C1FIFOBASET TRISCSET SPI1CONSET _DBG_CODE_SIZE IC5CONSET C1FIFOCI3INV CHELRU DCH1INTSET U3MODE C2FIFOUA25CLR C1FIFOCON18SET C2FIFOINT18CLR C2FIFOCON15SET Delay_MS C1FIFOCON24SET DCH2INTINV _on_reset I2C5TRNINV C1FIFOCON6 C1FIFOCON23INV DCH3CONCLR C1FIFOCON5 __vector_dispatch_37 U4BRGSET C2FIFOINT5CLR C2RXF21INV C1FIFOCON7 C1FLTCON6CLR __vector_dispatch_38 U1CONINV DCH3DSA DMAADDRCLR C1FIFOCON8 __vector_dispatch_35 C1FIFOCI14INV ETH_Init DCH0CPTRCLR DMASTATSET __vector_dispatch_36 IPC12 C2FLTCON1INV C1FIFOUA21SET DCH5INT CNPUESET DCH2ECONSET LATGINV IPC11 DCH5DSASET U1EP14CLR C1FIFOUA4SET C2FIFOUA15CLR DCH0DSACLR C1FIFOUA28 C1FLTCON1CLR C2FIFOCI5INV C2FIFOUA22INV U1IESET IPC4CLR C1FIFOCI28SET C1FIFOUA29 C2FLTCON6INV OC4CONSET C1FIFOUA10INV C1FIFOBAINV EMACxSUPPSET C2TMRSET C2RXF10SET C1CFGCLR AD1CHSCLR C2FIFOINT3SET BMXPUPBAINV __vector_dispatch_30 C1FIFOUA27 DCH7DSAINV _bss_end SPI2ASTATCLR C1RXF9CLR C2FIFOCI6SET C1FIFOUA26 U5MODEINV EMACxMAXFCLR DCH4SSACLR SPI1ACON U3BTXREG C1FIFOCON13SET C1RXF21CLR C2FIFOCI15 C1RXF8CLR C1FIFOCON12INV TMR2SET C1FIFOUA30SET C2FLTCON6SET U1EP0SET C2FIFOCI14 IC3CONSET U1EP4SET __vector_dispatch_32 DCH4INTINV U1CONCLR C1FIFOUA24 C1FIFOINT18INV C2FIFOCI16 __vector_dispatch_31 OC4RSCLR C2RXF21CLR C1RXF10CLR U1EP13CLR C2RXF31SET __vector_dispatch_34 C1FIFOUA25 C2FIFOCI17 OC3RSINV C2FIFOINT15SET C2FIFOUA22SET U2MODESET C2FIFOCI30CLR __vector_dispatch_33 C1FIFOCON3INV I2C2CONCLR C2FIFOCON22INV C1RXF20INV SPI3STATINV RSWRST C2FSTAT DCH5ECONINV EMAC1MAXFCLR C2FLTCON5CLR DCH3DPTRCLR C1FIFOUA23INV U6STA INTDisableInterrupts TMR5CLR DCH0SSIZ OSCCONSET C2FIFOUA13INV IC2CON PR23 DCH0SPTRCLR DCH1ECONCLR U1ASTA C2FIFOCI21SET DCH0DPTR C2RXF29SET ODCDINV C2FIFOUA6 SYSKEYINV C2FIFOUA5SET EMAC1SA0CLR DCH3ECON C1FIFOINT23INV C2FIFOUA9 U1ABRG C1FIFOINT28CLR LATFINV C2FIFOINT9CLR ODCEINV DCH4DPTRSET C2FIFOUA7 C2FIFOINT31 C1FLTCON3CLR C1RXF31INV IEC2 C2FIFOUA4 DCH6ECON C1FIFOUA10CLR U3STASET U3BSTASET C2FIFOINT21SET C1RXF29CLR C2FIFOUA5 IEC1 C2FIFOUA8 IPTMRCLR C2FIFOUA14INV C2RXF10CLR C1RXF29SET I2C3ADD EMACxSA2 DCH1SPTRCLR IEC0 EMAC1SA2INV C2FIFOINT26SET U1PWRCSET C2FIFOCI17CLR I2C5BRG C1FIFOCI4CLR C2FIFOCI26CLR EMACxSA1 C2FIFOUA4SET EMAC1MAXFINV C1RXF18CLR C1RXF18SET C2RXF18SET C2FIFOINT30 C1FIFOINT23SET EMACxSA0 C2RXF7INV SPI3BRG C2RXF23 T3CONINV I2C3ADDCLR C2FIFOUA11INV C1FIFOCI10INV DCH6CSIZCLR U1BMODESET NVMCONSET C1FIFOINT27INV U6TXREG C1FIFOINT26INV C1FIFOCI8SET ODCG PR1SET I2C2AADD DCH1CONSET C2FIFOCI0SET DCH4DATINV OC2RSCLR U6STACLR EMACxIPGTSET U1EP15INV DCH0CSIZ DCH3CPTRCLR EMACxSA1INV ODCGCLR DCH2DATCLR C1RXF11INV INTConfigureSystem EMACxMCFGINV EMAC1IPGRCLR OSCCONCLR C2RXF11CLR U1STAT PORTACLR C1FIFOUA19SET NVMSRCADDR C1FIFOINT19CLR IPC10CLR C2FIFOUA16SET C1FIFOUA23CLR T4CONCLR C2FLTCON7CLR OC5RSINV BMXDKPBASET I2C3ACONINV C1FIFOUA3SET CNENSET C2FIFOCI4INV C2FIFOUA11SET EMACxSA0INV C2FLTCON3 EMACxCLRTSET I2C4TRNINV DCH7INTINV C2FIFOCON6CLR TMR4CLR IC4CONINV I2C3STAT U1EP11CLR C1FIFOINT21 C2FLTCON6 C2RXF20 C1FIFOINT12INV C1RXM2SET C2FLTCON5 AD1CON3INV SPI2ABRG C1RXF20SET C1FIFOCI21INV DCH5SSIZ C2RXF22CLR C2FIFOCI14CLR PMCONSET DCH2SPTRSET I2C4ADDSET C2RXF22 _sbss_begin C2FLTCON7 SPI3ABRGINV C2RXF21 C2FIFOCON28INV C2FIFOINT17INV C1FIFOUA18CLR U2ABRGCLR C1FIFOINT29INV C1FIFOINT20 I2C5BRGSET C1RXF0SET C1FIFOCON31 DCH2CPTRINV I2C4TRNSET C1FIFOCI2INV SPI2ASTATINV C1FIFOINT25 C1FIFOINT22 DCH2CONSET EMAC1MCFGCLR C2RXF23CLR DCH3DSACLR DCH0DPTRSET I2C2ACONINV C2CONINV EMAC1MCMD U2BBRGSET C2FIFOINT13INV C1FIFOCI23INV C1FIFOINT24 DCH7DSIZ I2C5ADDSET C1FIFOCON30 C2FIFOCI12SET C1RXF17SET DCH5CONCLR C1RXF31SET U3MODEINV DCH6DSA C1FIFOCON11CLR U2ABRGSET I2C2AMSKSET I2C3ACON C1FIFOINT15INV I2C2ASTATINV C2RXF19SET C1FIFOINT29 EMAC1MWTD DCH6DATSET AD1PCFG C1FIFOINT26 C1FIFOINT27 C1RXF8INV IPC7INV PR5CLR C1FIFOINT23 C2FIFOCI20CLR C2FIFOUA24INV C2FIFOINT3 C1FIFOINT17CLR C1FIFOCI12INV C2FIFOCI19SET C2RXF12CLR IPC8CLR C1FIFOUA10 _APPO C2FIFOINT2 I2C5TRN C2RXF19CLR U6BRGSET C2FIFOCI23CLR I2C1AADD DCH1SSACLR I2C1BRGINV C1RXF0CLR U1OTGCONCLR DCH6SSIZINV C1FIFOCON22CLR I2C1AADDCLR PMMODE CVRCONINV C1FIFOCON20CLR C1FIFOCON13INV ETHSTAT C2FIFOCI11CLR U2STACLR C2FIFOCI6CLR _on_bootstrap EMACxTESTSET C1RXF6SET DCH7SSASET DCH2ECONINV C1FIFOCON27SET C2FIFOINT0 BMXDUPBACLR C1FIFOINT28 C1RXF4SET C2FIFOINT10SET C2VECINV C1RXF11SET AD1CON3SET C2FIFOCI13 C2FIFOCON21CLR TMR45 C1FIFOINT7SET SPI4BUF U1BRXREG C2FIFOCI28SET IPC6SET C1RXF20CLR C2FIFOINT1 I2C2CONSET C1FIFOCON21INV C2FIFOCI12 C1FIFOUA17SET C2FIFOCON11INV SPI2STATSET SPI1ABUF U1EP10SET U1EIRCLR C2FIFOUA30INV C2FIFOUA25INV C1FIFOCON24INV T2CON C2FLTCON7SET C1RXF28SET I2C2ACONSET T5CONSET DCH0INT I2C3ASTAT C1FIFOINT0CLR C2TMRCLR U2BSTA C1FIFOCI16 DCH1DSASET C2FIFOBACLR C1FIFOCI15 C2FIFOCI19 C2FIFOCI18 C1FIFOINT3SET DCH2CPTRCLR I2C1STATSET C1RXF31CLR C1FIFOCI17 I2C2ATRN ETH_Read_Packet C2FIFOCON14INVC2FIFOUA27SET C1FIFOCI18 C1RXM2CLR C1FIFOUA21INV TMR1INV C2FIFOCI10 C1FIFOCON16SET DMAADDR C1RXF30 U1FRMH DCH6DSIZ DCH1DPTRINV U1BDTP1 CHETAGCLR C1FIFOINT31CLR T3CON U1AMODE U3BMODESET C1FIFOCON10INV C1FIFOUA25SET C2FIFOINT24INV C2FIFOCON7CLR _data_end C1RXF22INV U3ABRGSET C1RXF31 I2C5ADD I2C2MSKSET C1RXF0 RSWRSTCLR OC5CONINV U1EP14INV C1RXF1 I2C3ATRNSET C2FIFOCI11 C1RXF16CLR DCH2SSIZ DCH2CONINV C2RXM3SET C1RXF8 AD1CON2 SPI2STATCLR EMAC1SUPPSET C1FIFOINT12SET C1RXF9 INTCONCLR C1RXF1CLR IFS1CLR U1EP7CLR C1RXF9INV C2FIFOCI31SET DCH6ECONINV C2FIFOINT7CLR C2RXF1SET ETHPMOINV C2FIFOINT28INV I2C1ACONSET TMR2INV C2FIFOUA30CLR RTCDATESET C1FIFOCON3SET CNPUEINV C2RXF15SET ODCFINV IEC2INV EMACxMAXFSET U1BTXREG U1BMODE C1RXF16SET ETHPMCSCLR SPI4CON DCH2DSIZCLR C2RXF1CLR T1CONCLR TRISFSET C2RXOVFSET CNEN DEVID DCH1DSIZINV I2C1ASTATINV C1RXF3 C1FIFOUA30INV ETHRXOVFLOW DCH2DSIZ DCRCDATASET PMAENINV I2C1ABRG ETHPMM1 EMACxSA0CLR C1RXF2 C1FIFOINT5SET C2FIFOCON25INV C2FIFOCON5CLR C2RXF8CLR C2FLTCON2SET C2FIFOINT8INV DCH7DSA EMAC1CFG1INV OC4CONINV C1RXF7 PMAENCLR Delay_US C1FIFOUA28CLR C2TMRINV SPI3ACON SPI3STATSET SPI3STATCLR C1FIFOCON29CLR C1RXF6 ETHPMM0 OC1RINV EMACxIPGTCLR OC5RINV C1FIFOCON19INV U2BTXREG C1RXF4 I2C4BRGCLR DCH0SPTRSET EMACxMADR C2FIFOCI10SET C1RXF22CLR C1RXF5 U1EP13INV CheKseg0CacheOff C2FLTCON5INV I2C1AMSK DCH3ECONCLR I2C3ASTATSET C1RXOVFSET DCH2DSASET U1EP8SET DCH4INTSET DCH1DSA C1FIFOINT5 DCH2INTCLR DCH1SSASET DCH5DSACLR C1FIFOUA15CLR C1FIFOUA10SET IC3CONINV DCH7SPTRINV DCH2DPTRINV U5STACLR U1FRML PMAEN DCH1INTCLR C2RXF23INV DCH3DPTRINV U1BBRGSET C2RXF26SET TMR1CLR C2RXF15CLR I2C2CON EMACxIPGRCLR C1FIFOINT6 C1FIFOCON3CLR C2FIFOUA25SET C1FIFOINT28INV C2FIFOINT4INV RTCTIMESET EMACxCFG1INV ETHPMM1INV C1FIFOCON18CLR I2C2TRNCLR I2C3RCV C1FIFOUA29CLR U1BBRGCLR I2C2BRG DCH2CSIZINV C1FIFOINT9INV C2FIFOCON26INV EMACxSUPPINV DCH0CPTR SPI1BRG C1FIFOINT9 DCH5SPTRINV C2FIFOCON19SET C2FIFOINT1SET C2FIFOUA14SET U1EIECLR C2CON C1FIFOUA12SET C2RXF5SET C1FLTCON1INV U1ADDRCLR PR3SET C1FIFOINT8 ETHHT1INV DCH6INTCLR CM1CONINV EMACxSA1CLR I2C4MSKINV C1FIFOINT7 ETH_PHY_Read U3BSTAINV IPC12CLR TMR4SET I2C3TRNSET DCH5SPTRCLR U1BSTAINV U3BSTACLR SPI2BRGCLR C1RXF22SET BMXDUPBASET C1FIFOCI0SET U3BBRGSET U3MODESET IC3CONCLR DCH2SPTR ADC1BUFB C1FIFOUA23SET C2FIFOCON4 U2AMODECLR C1FIFOCI21SET ETHIRQ C2RXF3SET ETHPMM1CLR C2FIFOINT30SET ADC1BUFC U5RXREG C2FIFOUA11CLR I2C3MSKSET C1RXF16INV C1FIFOINT19INV C1RXF2SET AD1CON1 DCH6SSIZSET I2C4CONCLR C1FIFOUA7SET ADC1BUFA ETHMCOLFRMSET LATDSET I2C3AADDCLR C1FIFOCI10SET C2FIFOUA20SET ADC1BUFF OC5RSET C2FIFOCON0 U1EP12SET C1FIFOCON29INV U2STAINV C1RXF11CLR TMR3INV C1RXM3CLR U1MODE U4MODECLR ETHPMM0INV IFS0CLR NVMCONINV ADC1BUFD C2FIFOCON1 SPI3ABRGCLR U1CONSET DCH1SSIZCLR ADC1BUFE DCH5ECONCLR BMXDUPBA C2FIFOCON27CLR INTSTAT EMACxCLRTINV U3BRGINV EMAC1CLRTCLR C1RXF27CLR C1FIFOCON20INV ETHHT0SET C1RXF19INV C1FIFOCON15INV C1FIFOCI14SET DCH7DSIZCLR DCH0ECONINV U1TOKINV DCH3INTSET C1FLTCON3INV C1FIFOCI14 C2FLTCON0INV C2FIFOCON21 C1RXF27SET SPI2STAT __vector_dispatch_39 IC4BUF C2FIFOCON14SET C2RXF0 C2RXF7 C1FIFOUA16CLR C1FIFOCI13 C2FIFOCON20 U2RXREG C1FIFOINT26SET C2RXF30CLR C2RXF8 PORTCCLR C2FIFOCON25 C2FIFOCON3 _STROINV IPC0 C2RXF30SET DCH1SPTRSET DCH5DATSET C2RXF23SET C2FIFOUA31SET DCH5CPTRINV DCH7ECONCLR PMSTATINV OC4CONCLR NVMCONCLR C2FIFOCON22 DCH7DPTRSET C1FIFOINT17INV OC2RSINV C2RXF28 DCH4DSIZSET IPC2 DCH6SSACLR SPI2BRG I2C1RCV C1FIFOCON6SET C2FIFOCON28CLR C2RXF27 AD1CON1INV DCH7SSA OC4R C2FIFOCON29 SPI3ASTATSET C2RXF2 IPC1 DCH0SSAINV C1FIFOCI19 C2FIFOCI15SET C2FIFOCON26 C2FIFOCON24 IPC8 C1FIFOCI4INV ALRMDATEINV U5STASET C2RXF1 ETHFRMTXOKSET OC1RSSET C1FIFOCI0INV C2RXF29 C2RXF25 PORTA DCH4CONINV IPC7 C2CFGINV C2FIFOCON27 C1FIFOCON11INV DCH5DSIZINV C2RXF6 DCRCXORINV I2C5MSK PORTC C2FIFOCON2 DCH2ECON C1RXF27INV CHEW0 DCH3DAT C2RXF26 EMAC1MWTDINV U6MODEINV SPI2ACONCLR C2FIFOCI2SET C2RXF5 U1AMODEINV DCH5SSASET IPC9 ETHPMM0CLR EMACxSA2CLR DCH5DPTRSET IC5BUF DCH7ECON I2C1BRGSET C1RXF0INV C2FIFOCON23 C2RXF3 C1FIFOCI10 PORTD IPC9CLR C1FLTCON5SET C1FIFOUA31INV ETHMCOLFRM C2RXF4 EMACxSA2INV C2FIFOCON25SET C2FIFOCI24SET C1FIFOCI17INV PORTB C1FIFOCI11 DCRCDATACLR C2FIFOINT3INV _general_exception_handler ETHRXFC DCH0SSASET PORTG C1FIFOCI12 DCH0SSACLR C2RXF9 C1FIFOCON22INV DCH3DSIZ C1RXM1SET IPC10INV C1FIFOUA8SET C2FIFOCON28 C2FIFOCI20SET ETHSCOLFRMSET U1SOF PORTE _STROSET C2RXF24 C1FIFOUA14CLR C2FLTCON7INV EMAC1IPGTINV PORTF CM1CON C1RXF25SET U1EP4CLR C1FIFOUA22INV C2FIFOCON12INV C1FIFOINT15SET I2C3MSK C1RXF14SET OC3RINV DCH6DSIZCLR C1FIFOCI28INV IPC6 C2FIFOCI6INV C1FIFOUA19 C2FIFOUA22CLR DCH2DATSET C1RXM2INV _DEBUGGER IPC5 SPI3BRGINV DCH1CSIZCLR C2FIFOCON16INV C1FIFOCON23CLR ETHRXFCCLR IPC4 C2FIFOCON20SET C1FIFOCON13CLR C1FIFOUA18 DCH1CSIZ C1FIFOCI13CLR RSWRSTSET C2RXF17SET IPC3 DCH0SSIZSET C2RXF17CLR C1FIFOUA17 SPI4BRGCLR C1RXF19CLR IFS0SET C2FIFOUA10CLR C2FIFOUA12CLR ODCGINV OC3RSET C1RXF2CLR U3TXREG C1FIFOUA28SET _persist_end C1FIFOUA1SET RTCALRMSET C1FIFOINT0INV DCH2DSIZSET C2RXM3CLR I2C4ADD DCH7CSIZSET ETHTXSTCLR U1OTGCONSET I2C1ACONINV C2FIFOBAINV DCH4SSAINV EMACxIPGRSET C1FIFOUA27CLR ETHHT0INV C2FIFOINT26INV EMACxMIND ETHPMOSET IPC4SET C1FIFOCI25SET I2C1TRNINV C2RXF30INV C1RXF3CLR I2C1AMSKINV I2C1ASTAT C1FIFOCON24CLR I2C1TRNSET U1PWRCCLR DCH3DPTRSET C2RXF28CLR C2RXF0CLR IPC0SET C2FIFOUA9SET C2TRECSET C2FIFOINT8CLR C2FIFOCI2INV C1FIFOINT2CLR C2FIFOUA19SET IPC11CLR CHETAG C2FIFOUA6INV C2FIFOCI3CLR C2FLTCON4INV AD1CHSSET C2FIFOUA12SET ALRMDATE C2FLTCON4 LATB C2RXF8INV EMAC1SA2SET C1FIFOCI24CLR DCH3ECONSET I2C1MSK LATA __vector_dispatch_63 __vector_dispatch_28 C2FLTCON0 C2FIFOUA5INV C2RXF28SET U2ASTACLR __vector_dispatch_29 LATD DCH1INT C2FIFOCI8INV C1FIFOCI6INV C1FIFOUA13CLR ETHTXST C2FIFOCI1SET ETHRXSTSET __vector_dispatch_61 __vector_dispatch_26 C2FLTCON2 LATC C1FIFOCON1SET __vector_dispatch_62 __vector_dispatch_27 C2TMR OC4RSINV EMACxCFG2INV I2C3BRGCLR C1FIFOUA19INV C2FLTCON1 _bmxdkpba_address _splim C1FIFOUA15SET C1VECINV I2C5RCV C2FIFOINT5 BMXDUDBACLR I2C3ARCV C2FIFOINT4CLR I2C3ASTATCLR DCH4SSIZ C2FIFOCI7CLR TMR2CLR U2AMODE EMAC1CLRTINV C2FIFOUA29SET EMACxSUPPCLR C2FIFOCI29 __vector_dispatch_21 EMAC1CFG2CLR C2RXF17INV DCH0DSAINV C2FIFOINT12INV DCH2SPTRCLR __vector_dispatch_20 TRISACLR C2INTSET DCH0SSIZINV C2RXF9SET C1RXF1INV C2RXF1INV DCH6SPTRSET C2FIFOCON2SET C2FIFOINT8 I2C3AMSKSET EMACxMRDD C2FIFOCON13CLR C2FIFOINT9 C2FIFOCI24 U4RXREG IC5CONINV SPI2CONINV U2BSTACLR C2FIFOINT7 __vector_dispatch_23 C2FIFOCI23 C2FIFOUA18INV C2FIFOINT4 __vector_dispatch_22 C2FIFOINT6 C1FLTCON6SET C1FIFOUA12 __vector_dispatch_60 __vector_dispatch_25 C1FLTCON0CLR C2FIFOCI25 C1TRECCLR C1FIFOUA11 C1FIFOINT13SET IC4CONCLR U4MODEINV I2C3AADD C1FIFOCON27CLR C2FIFOUA18SET __vector_dispatch_24 C2FIFOCI26 C2FIFOINT5SET IPC12INV U1AMODESET SPI4CONCLR EMAC1MCMDCLR LATBSET C2FIFOINT23INV C2CONCLR DCH3SPTRCLR C1RXF26SET SPI3ABRG C1FIFOUA15 AD1CHS C2FIFOCON31SET U1EP7 C1FIFOUA16 DCH2DATINV I2C5STATINV ETHFRMRXOK C1FIFOCON25CLR DCH4SPTR U1STASET SPI2ABUF DCRCCONINV C1FIFOUA14 DCH2SSIZSET __MIN_STACK_SIZE DCH0DPTRINV OC2RSSET DMACON C2RXF28INV C1FIFOUA13 _persist_begin C1FIFOCON16CLR DCH5SSA U1EP4 C2RXF2CLR C2FIFOUA17INV U1IECLR C1FIFOINT8INV SPI3ACONINV C2FIFOCON30INV I2C1AMSKSET I2C4CONSET C2FIFOUA23CLR C1FIFOCI19CLR C1FIFOCON28CLR U3BBRGCLR C1FLTCON4CLR U1EP9 CHETAGSET EMACxMRDDINV C1RXF19SET DCH3CON OC2CONCLR C1FIFOINT24SET SPI1CONCLR U1EP8 C1FIFOCI1CLR SPI3ACONSET ETHCON1CLR I2C4MSKSET C1FIFOCON0CLR C1FIFOCON6CLR C2FIFOCON5INV C2RXM0SET PORTFSET DCH1SSIZINV DCH6DPTRINV C2FIFOCI27INV DCH4ECON DCH6SSAINV ETHFRMTXOKINV C2FIFOCON16SET C2CFGCLR C1FIFOUA26CLR C2RXF12 C2FIFOCON25CLR I2C4BRGSET EMAC1IPGTCLR __DbgExecReturn AD1CON3 C2RXF13SET C1FLTCON2INV DCH0DSIZSET DCH4INT C2FIFOINT15INV C2VEC C1FIFOINT28SET U1BDTP3 C1TREC WDTCON C1FIFOCON14CLR IC4CON CM1CONCLR DCH1DAT C2FIFOUA23SET DCH3CPTRSET I2C4STATINV TMR3CLR U1BDTP1SET U1BDTP2 U1EP8INV DCH3CONINV U1BSTACLR PMADDRCLR SPI1ACONINV C2FIFOCI18INV ODCASET U1RXREG U1STA PORTDSET C2RXF24SET I2C1ATRNSET C1FIFOCI5CLR U3MODECLR C2FIFOCI2 C2FIFOCI1 DCH3CSIZCLR C1RXF15SET C1FIFOUA8INV C2FIFOCON6SET IPC7CLR PMDOUT I2C1ABRGINV C2FIFOCI3 C1RXF12SET C1TMRSET C2FIFOCI17SET C1FIFOCI30SET C1FIFOINT1INV C1FIFOCI27INV CHEMIS C2FIFOCON27SET C2FIFOCI4 C2RXF11 U2BMODESET C1RXM3INV C1FIFOINT30 C1FIFOINT31 C2FIFOCI5 C2RXF10 C2FIFOUA21CLR C1FIFOCI22CLR SPI4CONSET C1FIFOCON5SET U1BMODECLR C1FLTCON3SET DCH1SPTR __MPLAB_BUILD ETHFCSERR C1FIFOCI24INV C1FIFOCON30SET IFS1SET OC2CON C2FLTCON0SET C2FIFOCI17INV C2FIFOCI6 C1FIFOCON15CLR C2FIFOUA20CLR C2FIFOCI26SET C2FIFOCON9CLR RTCCONSET I2C4MSKCLR DCH5SSIZSET C1FIFOCI11CLR C2FIFOCI9INV DCH5CSIZCLR SPI2ACONSET U1OTGIEINV C1FIFOINT5CLR U1EP2 C1FIFOCON21 C1FIFOCON20SET I2C1TRNCLR U1OTGIESET IEC0CLR C2RXF27SET DCH5INTINV I2C1CONSET DCH0DSA I2C1STAT EMACxMAXF TRISBSET DCH5SSAINV U1EP0 DCH0DSIZCLR I2C3STATSET _gp DCH7SSIZCLR C1RXF30SET EMACxTESTCLR I2C1MSKINV C2FIFOCI26INV U3ASTASET RTCDATE C2FIFOINT9INV DCH0INTSET C1FIFOCON25 C2FIFOUA31CLR DCH3INTCLR _sdata_begin C2FIFOCON23INV C1FIFOCI16INV U1EP3 DCH0ECONCLR U1EP14SET I2C1ARCV U1EP6 C1FIFOCI13INV C2FLTCON3SET SPI1STATINV IPC10SET DCH2SSASET C2FIFOCI1CLR C1FIFOUA5SET U4BRGCLR C2FIFOINT19SET DCH7CSIZCLR DMACONCLR U1EP5 C1FIFOCI3CLR C2FIFOUA28INV U2MODECLR U2STA U3ABRG CNPUECLR SPI2ASTAT U1EP1 C2RXF16SET DCH1ECONSET C1FIFOCON26CLR TRISDCLR SPI1STATCLR C2FIFOCI21 C1FIFOCON20 C2FIFOCON20INV DCH6SSIZ C1FIFOCON22 C1RXF15CLR I2C2TRNINV C1RXF22 C1FIFOCON23 C2FIFOCI22 U1EP1SET DCRCDATAINV I2C4CON C1FIFOCON24 IPC11INV U3RXREG C2FIFOCON4INV U1AMODECLR C2FIFOUA0 DCH7ECONSET DCH4DSIZCLR EMACxMCMDINV EMACxMINDSET U1EP9INV C2FIFOUA3CLR U1TOKCLR DCH4CSIZSET C2FIFOCI3INV LATGSET C1RXF9SET SPI1ASTATINV C2FIFOUA29INV C2FIFOCON5 C1FIFOCON4CLR I2C3ABRGSET C1FIFOCON2SET C1FIFOCI26SET C2FIFOCI28 C2FIFOUA3 U4MODE C2FIFOCI5CLR U1BDTP2INV C1FIFOINT3CLR C1FIFOCI27 DCH3DSAINV C2FIFOCON6 U2ASTAINV U6RXREG C2FIFOCI4SET C1RXM1 C2FIFOUA2 DDPCON C2FIFOCI27 BMXCONINV C1FIFOCI26 C2FIFOUA1 T5CONCLR CHETAGINV C1RXM0 C2FIFOINT30INV SPI3BRGSET DCH6CPTRCLR OC4RCLR C1FIFOCI28 C2FIFOCON22SET SPI2CONSET ETHRXWM DCH5DPTRCLR IPC9SET C1FIFOCI29 C2FIFOCON9 C2FIFOCI16CLR SPI1BUF C2FIFOCI14INV C2FIFOCI20 C1FIFOUA25CLR C1RXF2INV DCH2SPTRINV C2FIFOCON8 C1RXF21 C1FLTCON5INV C1RXM2 U5BRGCLR C2RXF11INV C2FIFOCON4CLR C1RXF20 C1FLTCON2CLR I2C2MSKCLR C2FIFOCI23INV EMAC1MRDDCLR C2FIFOBASET C2FIFOCON7 U5BRG C1RXM3 C2FIFOINT25INV EMAC1SUPPINV ALRMTIMEINV INTCONSET DCH7CPTR DCH6SPTR C1RXF23SET C2FIFOCI25CLR C2FIFOCON5SET NVMADDR CVRCON C2FIFOCI7INV DCH3SSIZCLR DCH4DSIZ T1CONSET C2FIFOUA18CLR SPI1BRGSET C1FIFOCI2SET C1RXF26CLR DCH6DSIZSET C2RXF6INV DCH4ECONSET C2FIFOUA6SET TRISBCLR EMACxMRDDSET PMAENSET C1FIFOCON8CLR C2RXF0INV C2FIFOCON2INV ETHIRQINV I2C5CONINV C1FIFOCI7INV DCH7DSACLR EMAC1SA0SET DCH6CPTR C1FIFOUA27SET U1OTGSTAT C2FIFOINT0INV C1FIFOINT17SET I2C5MSKINV CMSTAT AD1CON2CLR U6BRGCLR SPI4CONINV CNCONCLR C2FIFOCI8SET DCH6CSIZ U1EP4INV EMAC1MCMDSET C1FIFOINT10CLR DCH6CON DCH5ECON CHECON PMDOUTCLR PMDOUTINV C2RXF27CLR C2FIFOUA8SET C1RXM1CLR T1CONINV C1FIFOCON23SET OC4CON C2FIFOCON31INV LATBINV C1FIFOCI16CLR _stack DCH4CONCLR U1ASTACLR EMAC1MCMDINV IEC2CLR DCH2SSAINV C2FIFOCI10INV DCH4DSA C1FIFOUA13INV TMR1SET U1EIEINV C1FIFOCON9CLR C1FIFOUA14SET EMAC1CFG2INV C1FIFOUA29SET I2C5BRGCLR SYSKEYCLR C1FIFOCI15SET CHEMSKINV BMXDUPBAINV C2FIFOCI4CLR DCRCCONCLR C2FIFOCON27INV C2FIFOCON0INV I2C2STAT C2FIFOCON29SET C1FIFOCON2CLR EMAC1IPGRINV C2FIFOINT21INV C1RXF10SET _sbss_end C2RXF20SET LATDINV CM2CONSET C2FIFOCI27SET OC3RSCLR C1FIFOCI1INV __vector_dispatch_8 C1RXF28CLR C1FIFOUA12CLR C2CFG C1FIFOCI14CLR DCH1DSAINV U1ASTAINV EMAC1MCFGINV C1FIFOCI9SET C1FIFOUA17INV SPI1CON ETHCON1SET DCH7DPTRINV __vector_dispatch_6 IPC11SET U1BDTP1INV C1FIFOCON12SET C1FIFOCI27CLR C1FIFOCI5INV INTEnableInterrupts C2FIFOCON3INV DCH0DATINV C1RXF24CLR EMACxTESTINV PORTAINV C1RXF29INV OC5RCLR U4MODESET C1FIFOCON17CLR I2C1BRG C1RXF26INV C1FIFOCI6SET C2FIFOINT2CLR DCH4CPTRSET C1RXF18INV U2STASET I2C2BRGINV I2C5BRGINV C1FIFOCI25CLR EMACxMCFGCLR C2RXF31INV TRISDSET PMSTAT C2RXF29CLR EMACxCFG1SET ETHALGNERRINV DCH5SSIZCLR U1EP6CLR C2FIFOINT7INV __vector_dispatch_7 BMXDKPBAINV I2C2ACON C2RXF25CLR DCH7SSIZINV C2FIFOINT14INV C1FIFOUA7CLR PR2SET DCH1INTINV C2FIFOCI18SET CHEW1 C1FIFOUA2SET U3STA C1FIFOUA16SET CHEW2 U1EP5INV I2C2ABRGSET C1RXF6CLR LATDCLR C1FIFOCI2CLR C2RXF8SET OC3R C2RXM2CLR OC1RSCLR CHEW3 C1FIFOUA26INV SPI3ACONCLR C2RXF29INV C1FIFOCON7INV C1FIFOINT11SET C2FIFOCON9INV C2FIFOUA29CLR SPI1ASTAT DCH4ECONCLR C1RXF13CLR C1RXF17CLR C1FIFOINT1CLR CM2CONCLR DCH5DSAINV _RESET_ADDR CHECONINV C1FIFOINT21CLR DCRCXORCLR U1EP3CLR TRISFCLR VA_TO_PA C1FIFOCI25 _SPLIM C1FIFOCI24 OC3CONINV EMACxMWTDSET OC3CONCLR C2FIFOCON30 C2FIFOCI31INV I2C5STAT IC2BUF C2FIFOCON31 ETHALGNERR DCH1DSIZSET C1RXF21SET DCH3CSIZSET U1IRCLR C1RXM0CLR C2FIFOINT14CLR C1FIFOUA9INV C1RXF17INV _min_stack_size ETHCON2 C2RXF6SET C2RXF19 DCH0SSIZCLR C2RXF4CLR C2RXF18INV I2C4CONINV C1FLTCON4 U1STAINV C1TMRINV ETHPMCSINV U4BRG BMXCON C2RXF17 C2FLTCON5SET I2C3STATCLR C2FIFOCON13INV ETH_PHY_Write C1CFG ETHIENSET C2RXF16 C1FLTCON5CLR WDTCONSET C1FIFOCON1INV U1BDTP3SET C2CFGSET DCH5ECONSET DCH0DSIZ C1RXF5CLR C2RXF5CLR C2RXF18 C1FIFOCON17INV PR2INV C1FLTCON6 C2RXF14 C2FIFOINT10INV U1OTGIRCLR ETHRXWMINV C1FIFOUA8 U3AMODECLR C1FIFOUA20SET DCH2INTSET U4STASET U2BRGINV C1FLTCON7 C1FIFOUA9 C2RXF15__vector_dispatch_9 C1FLTCON7CLR INTCONINV C1FIFOUA25INV C1FIFOINT0SET __vector_dispatch_0 U1ADDR DCH5DPTR C1FIFOCI21 C2FIFOINT28SET DCH0SSA SPI3CONCLR C1FIFOINT20CLR C2FIFOCON28SET IPC7SET I2C4ADDCLR I2C2ADDCLR DCH7SSAINV C1FIFOCI20 C1FIFOCI23 C2FIFOCI1INV __vector_dispatch_4 DCH3SPTR C1FIFOCI22 C2FIFOINT1CLR DCH7SPTR __vector_dispatch_1 ETHPMOCLR EMAC1MIND DCH7DAT C1RXF7INV C2FIFOUA1SET I2C3AMSKINV DCH2SSIZINV SPI4STATSET C2RXF27INV DCH6SSIZCLR EMACxTEST DCH3SSIZ CM1CONSET TMR1 U2BRGCLR C2FLTCON2CLR DCH3CONSET C1FIFOCON5INV I2C1AADDINV DCH6DPTRCLR TMR2 __vector_dispatch_3 C1RXF3INV RTCDATEINV C2RXF13 U1OTGCON DCH3SSASET DCH7CSIZINV SPI1ACONCLR TMR3 I2C3ACONCLR IPC2INV __vector_dispatch_2 C2RXF22SET C2VECSET __vector_dispatch_5 U1ATXREG DCH4DATCLR DCH7INT EMAC1MRDDINV C2FIFOUA15 ODCDSET IC1CONCLR C2RXM3INV C1INTSET C1RXF15INV I2C1ABRGCLR DCH5CPTRSET DCH4CSIZINV C2FIFOINT30CLR C2FIFOUA14 C1FLTCON5 DCH3ECONINV DCH5SSIZINV ETHCON1 CHEHIT C2RXF16INV C2FIFOCON8INV C1FIFOINT5INV C1FLTCON2 ETHALGNERRSET SPI2ABRGINV U3ASTAINV C1FLTCON3 I2C1ADDINV C1FLTCON1 SPI1ASTATCLR C1FSTATINV T2CONCLR C1FIFOCON9INV IC2CONINV U1EP1CLR I2C5CONSET C1RXF14CLR I2C1STATCLR PMMODESET IC2CONCLR __vector_dispatch_11 C2FIFOUA11 IPC0INV C2FIFOUA10 PR4SET C2FIFOCI13INV DCH5INTCLR C1FLTCON0 __vector_dispatch_10 DCH0CPTRSET U5MODE C2FIFOUA12 U1EP1INV IC1CONINV C1FIFOCON26 C2FIFOUA13 C2FIFOCI8 DCH4INTCLR DCH7CONINV C2FIFOCI9 C2FIFOINT25CLR SPI1ABRGINV C1FLTCON0SET BMXDUDBAINV IC1CONSET ALRMTIMECLR U1ADDRSET IFS1 DCH5CSIZSET PORTGSET BMXCONCLR C1INTINV C1FIFOINT2SET PORTGCLR SPI4STAT __vector_dispatch_57 C1FIFOCON29 DCH6SPTRCLR ETHTXSTSET IFS2 C1RXF25CLR C2FIFOCI7 C2FIFOCI0 __vector_dispatch_59 T3CONCLR C2FIFOUA4INV __vector_dispatch_58 WDTCONINV IPC0CLR AD1CON2INV U1ADDRINV ODCBCLR C1FIFOCON28 C2FIFOUA28CLR C2FIFOCI22INV C1FIFOCON27 SPI2STATINV T4CONINV C2FIFOCON18SET EMAC1MADR OC5CONCLR C1RXF29 C2FIFOINT31INV I2C4ADDINV U5TXREG DCH5DSA C2FIFOINT17SET C1FIFOUA12INV INTCON DCH5CPTR C1RXF27 __ETH_Interrupt_Handler U1BSTA C2RXF26CLR LATCINV C1RXF26 SPI3CONSET RTCALRMCLR DCH2DSAINV C2FIFOCON26CLR DCH7SPTRCLR C1FIFOINT22SET C1RXF28INV DCH0DAT C2FIFOCI0CLR C1RXF28 ETHIRQCLR C1RXF24 C2FIFOINT12CLR __vector_dispatch_52 U3BBRGINV DCH2ECONCLR C1FIFOINT20SET U6BRG DCH1DATINV C2FIFOINT20INV I2C1BRGCLR C1RXF23 __vector_dispatch_51 C1RXF25 AD1CSSLSET C1FIFOINT10INV C2FIFOCON1INV U1ABRGSET C2FIFOCI16SET TRISB I2C3MSKINV __vector_dispatch_15 C1RXOVFCLR U1PWRCINV __vector_dispatch_56 __vector_dispatch_13 __vector_dispatch_50 U2TXREG DCH0SPTR U1EP13SET SPI1BRGCLR C2FIFOINT3CLR TRISD __vector_dispatch_14 BMXPUPBA TMR4 __vector_dispatch_55 EMAC1SUPP C2FIFOCON13SET __vector_dispatch_12 EMAC1MCFGSET C1CONSET BMXDUDBASET OC3CON __vector_dispatch_54 TMR5 TRISA ETHRXWMSET TRISE __vector_dispatch_53 C1FIFOINT23CLR DCH4SPTRSET PR4INV C1FIFOCON27INV C2FIFOCI25SET C2FIFOCI13SET T1CON C2FIFOCON21SET __vector_dispatch_17 C2RXF2INV U6STAINV __vector_dispatch_19 TRISC ETHALGNERRCLR C1FIFOINT13CLR __vector_dispatch_16 I2C2TRN __vector_dispatch_18 C1FIFOINT4INV EMACxSA0SET C1RXF7SET U2ATXREG C2FIFOINT2INV IPC5INV DCH1DSACLR DCH0DATCLR C2FIFOUA0CLR C2FIFOCI30INV U4STAINV C2RXF6CLR DCH4CPTRINV TRISF U6MODE DCH4CSIZCLR C2FLTCON1CLR PORTEINV ETHHT1SET TRISG C2FIFOUA17CLR EMACxIPGRINV NVMKEY IPTMR C1FIFOUA0SET DCH2SSIZCLR I2C2ARCV C2FIFOINT11 C1FIFOINT16CLR CHEPFABT C1FIFOINT27SET C1FIFOCI24SET C2RXF14CLR EMAC1MINDSET PORTASET C2FIFOINT10 C2FIFOCON10SET C1FIFOBACLR C1FIFOINT21INV C1FIFOCI21CLR TRISCINV T4CON ETHRXFCINV ETHSCOLFRMCLR PORTFINV U1EP5CLR C2FIFOINT12 _end DCH5CSIZINV DCH5SPTR C2FIFOINT1INV C2FIFOINT23CLR C1FLTCON1SET TRISGCLR IEC0INV DCRCCON C1FIFOCI18CLR IPC1SET OC1RS C1FIFOUA7INV DCH0ECON C2CONSET C2FIFOUA2INV C2FIFOINT19 U2BRXREG I2C2BRGSET C2FIFOINT14 C2FIFOINT4SET PR45 U1MODECLR U3BMODECLR U1IEINV ETHHT1CLR C2FSTATSET C1FIFOUA5CLR C1FIFOINT4CLR DCH0CSIZINV C1FIFOUA13SET C1FIFOCI10CLR IPC3SET C1FIFOUA2INV ETHSTATINV C2FIFOCI29INV C2FIFOINT15 C1FIFOCI7CLR C1FIFOCI13SET DCH5DAT U1ASTASET C1FIFOCI29CLR I2C1ASTATSET C2FIFOINT13 DCH1DPTRSET C2RXF31CLR C2FIFOCON3CLR CVRCONCLR I2C2ASTAT TMR3SET TRISGSET C2FIFOCI7SET I2C2STATINV OC1RSINV LATFCLR C2FLTCON1SET U1OTGIECLR C1FIFOINT30INV C2FIFOINT16 DCH7DATINV U2MODE C1FIFOCON26INV C2FIFOINT17 DCH2CSIZCLR C2FIFOCON2CLR PR1 C1FIFOCON28INV OC1CON C1FIFOCON17SET EMACxMCFG PR4 C1FIFOCON1CLR CHECONCLR C2FIFOCON17SET DCH6CONCLR C2FIFOCI29SET C1FIFOCI15CLR _APPI TRISESET DCH0INTCLR PR3 I2C2ATRNCLR OC1CONCLR DCH6INT I2C2AADDCLR C1FIFOINT16SET OSCTUN OC2RINV U5MODESET U1STACLR I2C3CONINV NVMADDRSET DCH6DAT C2RXF19INV TRISEINV C2FIFOUA26SET C1FIFOCI23CLR C2FIFOINT18 __exception_handler_break C1FIFOCON28SET TRISAINV C1FIFOCON10 I2C2BRGCLR EMAC1MAXF EMACxSUPP C1FIFOCI26CLR ODCFSET C2FIFOCI11INV C2RXF15INV C2FIFOCI20INV C2FIFOCI11SET C1FLTCON6INV PMDININV IEC1SET U2MODEINV C1FIFOINT27CLR TMR5SET IPC2CLR C2RXF12SET LATGCLR PR5 DCH4DSAINV I2C5ADDINV C1RXM1INV C1FIFOUA31 U1EP3INV U3BRGSET DCH4SSIZINV OC4RINV C1FIFOCON14 DCH1DSIZ C2FIFOINT20CLR PORTGINV EMACxCFG1 DCH3SPTRSET U1OTGCONINV C1FIFOUA26SET C1FIFOUA18INV C1FIFOINT24CLR I2C2ACONCLR EMACxCFG2 WDTCONCLR DCH7DSASET C2FIFOINT26CLR DCH1CONCLR DCH6DSASET T5CONINV LATAINV LATBCLR IEC0SET C1FIFOCI12CLR __pic32_software_reset ETHCON1INV C1RXF3SET EMAC1CFG2SET C2FIFOUA19CLR C2FIFOINT15CLR U2ASTASET EMACxSA2SET C1FIFOCON11 DCRCDATA IFS0 C1FIFOUA30 I2C3CON C1RXF7CLR C2FIFOCI19INV SPI1STATSET CMSTATSET DCH6INTINV C1FIFOINT31SET C1FIFOCON12 C1RXF11 I2C3ATRN ETHCON2SET PR1INV PR2 C2FIFOUA8INV I2C1TRN C1FIFOCON13 C2RXF26INV EMAC1TEST CNPUE C1FIFOINT12CLR TMR23 DCH0CONINV EMAC1CLRT DCH2DSA I2C2AMSKCLR C1FIFOUA31SET I2C2RCV U1EP6INV EMAC1IPGTSET DCH6CPTRSET C1FIFOINT18CLR C2FIFOUA27INV C1FIFOCON21CLR ETH_Write_Packet C2FIFOINT31CLR DCH1CPTRCLR DCH5CPTRCLR C2FIFOINT12SET C1FIFOCON14SET DCH1SSIZSET C1FIFOINT2INV U2ASTA C1FIFOUA18SET BMXPUPBACLR C2FIFOINT23SET CHEACCINV U1EIE C2FIFOUA16INV C1FIFOCI5SET C2FIFOUA30SET C2RXM2INV LATE C1FIFOINT6SET OC2RS C2FIFOCI28INV CHEMSK LATF C1FIFOUA6CLR RSWRSTINV C1FIFOUA22SET C2FIFOCI30 C2FIFOUA15SET