Rev 248 | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed
#define ADXL345_LOW_POWER_MODE// Chip Address#define ADXL345_ADDRESS (0x53) // Assumes ALT address pin low// Register Defines#define ADXL345_REG_DEVID (0x00) // Device ID#define ADXL345_REG_THRESH_TAP (0x1D) // Tap threshold#define ADXL345_REG_OFSX (0x1E) // X-axis offset#define ADXL345_REG_OFSY (0x1F) // Y-axis offset#define ADXL345_REG_OFSZ (0x20) // Z-axis offset#define ADXL345_REG_DUR (0x21) // Tap duration#define ADXL345_REG_LATENT (0x22) // Tap latency#define ADXL345_REG_WINDOW (0x23) // Tap window#define ADXL345_REG_THRESH_ACT (0x24) // Activity threshold#define ADXL345_REG_THRESH_INACT (0x25) // Inactivity threshold#define ADXL345_REG_TIME_INACT (0x26) // Inactivity time#define ADXL345_REG_ACT_INACT_CTL (0x27) // Axis enable control for activity and inactivity detection#define ADXL345_REG_THRESH_FF (0x28) // Free-fall threshold#define ADXL345_REG_TIME_FF (0x29) // Free-fall time#define ADXL345_REG_TAP_AXES (0x2A) // Axis control for single/double tap#define ADXL345_REG_ACT_TAP_STATUS (0x2B) // Source for single/double tap#define ADXL345_REG_BW_RATE (0x2C) // Data rate and power mode control#define ADXL345_REG_POWER_CTL (0x2D) // Power-saving features control#define ADXL345_REG_INT_ENABLE (0x2E) // Interrupt enable control#define ADXL345_REG_INT_MAP (0x2F) // Interrupt mapping control#define ADXL345_REG_INT_SOURCE (0x30) // Source of interrupts#define ADXL345_REG_DATA_FORMAT (0x31) // Data format control#define ADXL345_REG_DATAX0 (0x32) // X-axis data 0#define ADXL345_REG_DATAX1 (0x33) // X-axis data 1#define ADXL345_REG_DATAY0 (0x34) // Y-axis data 0#define ADXL345_REG_DATAY1 (0x35) // Y-axis data 1#define ADXL345_REG_DATAZ0 (0x36) // Z-axis data 0#define ADXL345_REG_DATAZ1 (0x37) // Z-axis data 1#define ADXL345_REG_FIFO_CTL (0x38) // FIFO control#define ADXL345_REG_FIFO_STATUS (0x39) // FIFO status#define ADXL345_MG2G_MULTIPLIER (0.004) // 4mg per lsb#define ADXL_BYTE_READ (0x80)#define ADXL_BYTE_WRITE (0x80)#define ADXL_MULTI_BYTE_READ (0xC0)// Register values for ADXL345_REG_BW_RATEtypedef enum{#ifndef ADXL345_LOW_POWER_MODEADXL345_DATARATE_3200_HZ = 0xF, // 1600Hz Bandwidth 140µA IDDADXL345_DATARATE_1600_HZ = 0xE, // 800Hz Bandwidth 90µA IDDADXL345_DATARATE_800_HZ = 0xD, // 400Hz Bandwidth 140µA IDDADXL345_DATARATE_6_25HZ = 0x6, // 3.13Hz Bandwidth 45µA IDDADXL345_DATARATE_3_13_HZ = 0x5, // 1.56Hz Bandwidth 40µA IDDADXL345_DATARATE_1_56_HZ = 0x4, // 0.78Hz Bandwidth 34µA IDDADXL345_DATARATE_0_78_HZ = 0x3, // 0.39Hz Bandwidth 23µA IDDADXL345_DATARATE_0_39_HZ = 0x2, // 0.20Hz Bandwidth 23µA IDDADXL345_DATARATE_0_20_HZ = 0x1, // 0.10Hz Bandwidth 23µA IDDADXL345_DATARATE_0_10_HZ = 0x0, // 0.05Hz Bandwidth 23µA IDD (default value)#endifADXL345_DATARATE_400_HZ = 0xC, // 200Hz Bandwidth 140µA IDD / 90uA LPADXL345_DATARATE_200_HZ = 0xB, // 100Hz Bandwidth 140µA IDD / 60uA LPADXL345_DATARATE_100_HZ = 0xA, // 50Hz Bandwidth 140µA IDD / 50uA LPADXL345_DATARATE_50_HZ = 0x9, // 25Hz Bandwidth 90µA IDD / 45uA LPADXL345_DATARATE_25_HZ = 0x8, // 12.5Hz Bandwidth 60µA IDD / 40uA LPADXL345_DATARATE_12_5_HZ = 0x7 // 6.25Hz Bandwidth 50µA IDD / 35uA LP} dataRate_t;// Register values for ADXL345_REG_DATA_FORMATtypedef enum{ADXL345_RANGE_16_G = 0x3, // +/- 16gADXL345_RANGE_8_G = 0x2, // +/- 8gADXL345_RANGE_4_G = 0x1, // +/- 4gADXL345_RANGE_2_G = 0x0 // +/- 2g (default value)} range_t;unsigned char ADXLInit(void);void ADXLStandbyOn(void);void ADXLStandbyOff(void);void ADXLInitInterrupts(void);void ADXLClearInterrupts(void);void ADXLRead(int *x, int *y, int *z);void ADXLSetRange(range_t range);void ADXLSetDataRate(dataRate_t rate);