| 30,14 → 30,15 |
|---|
| SSP2STATbits.SMP = 0; // Input is sampled in the middle of data output time |
| SSP2STATbits.CKE = 0; // Transmit occurs on transition from Idle to active clock state |
| |
| if (speed == SPI2_FOSC_4) |
| SSP2CON1bits.SSPM = 0b0000; // Clock = FOSC/4 |
| else if (speed == SPI2_FOSC_8) |
| SSP2CON1bits.SSPM = 0b1010; // Clock = FOSC/8 |
| else if (speed == SPI2_FOSC_16) |
| SSP2CON1bits.SSPM = 0b0001; // Clock = FOSC/16 |
| else |
| SSP2CON1bits.SSPM = 0b0010; // Clock = FOSC/64 |
| SSP2CON1bits.SSPM = speed; |
| // if (speed == SPI2_FOSC_4) |
| // SSP2CON1bits.SSPM = 0b0000; // Clock = FOSC/4 |
| // else if (speed == SPI2_FOSC_8) |
| // SSP2CON1bits.SSPM = 0b1010; // Clock = FOSC/8 |
| // else if (speed == SPI2_FOSC_16) |
| // SSP2CON1bits.SSPM = 0b0001; // Clock = FOSC/16 |
| // else |
| // SSP2CON1bits.SSPM = 0b0010; // Clock = FOSC/64 |
| |
| SSP2CON1bits.CKP = 1; // Idle state for clock is a high level |
| SSP2CON1bits.SSPEN = 1; // Enable MSSP module |