| 0,0 → 1,59 |
|---|
| #ifndef GYRO_L3G_H |
| #define GYRO_L3G_H |
| |
| // Device Types |
| #define L3G4200D_DEVICE 0 |
| #define L3GD20_DEVICE 1 |
| |
| // SA0 States |
| #define L3G_SA0_LOW 0 |
| #define L3G_SA0_HIGH 1 |
| |
| // Slave Addresses |
| #define L3G4200D_ADDRESS_SA0_LOW (0xD0 >> 1) |
| #define L3G4200D_ADDRESS_SA0_HIGH (0xD2 >> 1) |
| #define L3GD20_ADDRESS_SA0_LOW (0xD4 >> 1) |
| #define L3GD20_ADDRESS_SA0_HIGH (0xD6 >> 1) |
| |
| // Register Addresses |
| #define L3G_WHO_AM_I 0x0F |
| |
| #define L3G_CTRL_REG1 0x20 |
| #define L3G_CTRL_REG2 0x21 |
| #define L3G_CTRL_REG3 0x22 |
| #define L3G_CTRL_REG4 0x23 |
| #define L3G_CTRL_REG5 0x24 |
| #define L3G_REFERENCE 0x25 |
| #define L3G_OUT_TEMP 0x26 |
| #define L3G_STATUS_REG 0x27 |
| |
| #define L3G_OUT_X_L 0x28 |
| #define L3G_OUT_X_H 0x29 |
| #define L3G_OUT_Y_L 0x2A |
| #define L3G_OUT_Y_H 0x2B |
| #define L3G_OUT_Z_L 0x2C |
| #define L3G_OUT_Z_H 0x2D |
| |
| #define L3G_FIFO_CTRL_REG 0x2E |
| #define L3G_FIFO_SRC_REG 0x2F |
| |
| #define L3G_INT1_CFG 0x30 |
| #define L3G_INT1_SRC 0x31 |
| #define L3G_INT1_THS_XH 0x32 |
| #define L3G_INT1_THS_XL 0x33 |
| #define L3G_INT1_THS_YH 0x34 |
| #define L3G_INT1_THS_YL 0x35 |
| #define L3G_INT1_THS_ZH 0x36 |
| #define L3G_INT1_THS_ZL 0x37 |
| #define L3G_INT1_DURATION 0x38 |
| |
| typedef struct { |
| char address; |
| } L3G_DATA; |
| |
| void L3G_Init(L3G_DATA *data, char device, char sa0); |
| void L3G_Begin(void); |
| void L3G_Read(int *x, int *y, int *z); |
| |
| #endif |
| |