41,6 → 41,7 |
SSP1STAT = 0x0; |
SSP1CON1 = 0x0; |
SSP1CON2 = 0x0; |
SSP1CON3 = 0x0; |
SSP1CON1bits.SSPM = 0x8; // I2C Master Mode |
if (speed == 0x01) { |
SSP1ADD = 0x13; // Operate at 400KHz (32MHz) |
134,9 → 135,12 |
SSP1STAT = 0x0; |
SSP1CON1 = 0x0; |
SSP1CON2 = 0x0; |
SSP1CON1bits.SSPM = 0xE; // Enable Slave 7-bit w/ start/stop interrupts |
SSP1CON3 = 0x0; |
SSP1CON1bits.SSPM = 0x6; // Enable Slave 7-bit address |
SSP1STATbits.SMP = 1; // Slew Off |
SSP1CON2bits.SEN = 1; // Enable clock-stretching |
SSP1CON3bits.PCIE = 1; // Interrupt on stop condition |
SSP1CON3bits.SCIE = 0; // Disable interrupt on start condition |
SSP1CON1bits.SSPEN = 1; // Enable MSSP1 Module |
} |
|
349,7 → 353,6 |
// Read SPPxBUF if it is full |
if (SSP1STATbits.BF == 1) { |
received_data = SSP1BUF; |
// DBG_PRINT_I2C("I2C: data read from buffer: %x\r\n", SSP1BUF); |
data_read_from_buffer = 1; |
} |
|
357,20 → 360,21 |
switch (i2c_data_p->operating_state) { |
case I2C_IDLE: |
{ |
// Ignore anything except a start |
if (SSP1STATbits.S == 1) { |
i2c_data_p->buffer_in_len_tmp = 0; |
i2c_data_p->operating_state = I2C_STARTED; |
} |
break; |
} |
case I2C_STARTED: |
{ |
// // Ignore anything except a start |
// if (SSP1STATbits.S == 1) { |
// i2c_data_p->buffer_in_len_tmp = 0; |
// i2c_data_p->operating_state = I2C_STARTED; |
// } |
// break; |
// } |
// case I2C_STARTED: |
// { |
// In this case, we expect either an address or a stop bit |
if (SSP1STATbits.P == 1) { |
// Return to idle mode |
i2c_data_p->operating_state = I2C_IDLE; |
} else if (data_read_from_buffer) { |
i2c_data_p->buffer_in_len_tmp = 0; |
if (SSP1STATbits.D_nA == 0) { |
// Address received |
if (SSP1STATbits.R_nW == 0) { |
384,7 → 388,7 |
} |
} else { |
i2c_data_p->operating_state = I2C_IDLE; |
i2c_data_p->return_status = I2C_ERR_NODATA; |
i2c_data_p->return_status = I2C_ERR_NOADDR; |
} |
} |
break; |