179,14 → 179,14 |
|
ETHIENbits.TXBUSEIE = 1; // Enable interrupt on transmit BVCI bus error |
ETHIENbits.RXBUSEIE = 1; // Enable interrupt on receive BVCI bus error |
// ETHIENbits.RXDONEIE = 1; // Enable interrupt on packet received |
ETHIENbits.PKTPENDIE = 1; // Enable interrupt on packet pending |
ETHIENbits.RXDONEIE = 1; // Enable interrupt on packet received |
// ETHIENbits.PKTPENDIE = 1; // Enable interrupt on packet pending |
// ETHIENbits.RXACTIE = 1; |
ETHIENbits.TXDONEIE = 1; // Enable interrupt on packet sent |
ETHIENbits.TXABORTIE = 1; // Enable interrupt on packet send aborted |
|
IPC12bits.ETHIP = 2; // Set interrupt priority to 2 |
IPC12bits.ETHIS = 2; // Set intererupt sub-priority to 2 |
IPC12bits.ETHIP = 1; // Set interrupt priority to 2 |
IPC12bits.ETHIS = 1; // Set intererupt sub-priority to 2 |
IEC1bits.ETHIE = 1; // Enable ethernet interrupts |
|
EMAC1SUPPbits.RESETRMII = 0; // Bring the RMII module out of reset |
233,10 → 233,10 |
|
// Read the packet data values into the buffer |
size = eth_data->RX_ED_table.descriptor[descriptor_index].BYTE_COUNT - 18; |
*length = size; |
for (j = 0; j < size - 18; j++) { |
for (j = 0; j < size; j++) { |
buffer[j] = eth_data->RX_ED_buffer[descriptor_index][j+14]; |
} |
*length = size; |
|
// Reset the descriptors |
eth_data->RX_ED_table.descriptor[descriptor_index].SOP = 0; |
307,7 → 307,7 |
} |
|
void __ISR(_ETH_VECTOR, ipl1) __ETH_Interrupt_Handler(void) { |
uint32_t value = ETHIRQ; |
// uint32_t value = ETHIRQ; |
if (ETHIRQbits.TXBUSE) { |
|
ETHIRQbits.TXBUSE = 0; |
316,14 → 316,15 |
|
ETHIRQbits.RXBUSE = 0; |
} |
// if (ETHIRQbits.RXDONE) { |
// ETHIRQbits.RXDONE = 0; |
// } |
if (ETHIRQbits.PKTPEND) { |
if (ETHIRQbits.RXDONE) { |
if (eth_data->rx_callback != NULL) |
(*eth_data->rx_callback)(); |
ETHIRQbits.PKTPEND = 0; |
ETHIRQbits.RXDONE = 0; |
} |
// if (ETHIRQbits.PKTPEND) { |
// |
// ETHIRQbits.PKTPEND = 0; |
// } |
if (ETHIRQbits.TXDONE) { |
if (eth_data->tx_callback != NULL) |
(*eth_data->tx_callback)(); |